Introduction to FP8 Formats: part 1. The rationale behind 8-bit floating-point data formats, their ecosystem momentum, and hardware support. November 12th, 2026 - By: Siyu Mou The industry is moving from high-precision formats (FP32, FP16, BF16) to lower-precision data types for Machine Learning (ML) inference and training. In cloud and data center environments, lower-precision data types deliver higher throughput by packing more compute per cycle from the same platform. On edge and mobile devices, smaller formats reduce model size, memory footprint and bandwidth, which directly affects power consumption and latency. Arm, Intel, and NVIDIA published an OCP 8-bit Floating Point Specification (OFP8). It is an interchange format that allows software systems to share the models easily. FP8 is not a future concept, it is being deployed today. It is already supported by NVIDIA's Hopper H100 GPU, with software deployment appearing in major ML frameworks. Arm added the FP8 support to the Arm v9 ISA and is exploring the best way to integrate the FP8 across all the ML platforms. This blog post explains the FP8 data formats, the new Floating-point Mode Register (FPMR), and the instruction set that makes FP8 practical on Arm CPUs. FP8 data format. Unlike IEEE FP64, FP32, and FP16, FP8 is not a single format, it is a family. The whitepaper FP8 Formats for Deep Learning proposes an FP8 format consisting of two encodings: E4M3 and E5M2. Why a family of formats? With only 8 bits available, FP8 makes a trade-off between precision and dynamic range. A single encoding cannot fit all tensors equally well. Activations and weights usually have a smaller and more stable value distribution after training or calibration. They can therefore benefit from more mantissa bits, which help represent nearby values more precisely. Gradients can change much more during forward and backward passes. They can therefore benefit from more exponent bits and a larger dynamic range, which helps avoid overflow or underflow. The two encodings enable software to choose the right format for each tensor role. Use E4M3 when precision is more important and use E5M2 when dynamic range is more important. This is the key idea from FP8, and Arm reflects the same idea in the FPMR register. With FPMR, each source operand can independently select which FP8 format it uses. Supported data types. | / | E4M3 | E5M2 | | Exponent bits | 4 | 5 | | Mantissa bits | 3 | 2 | | Bias | 7 | 15 | | Max normal value | 448 | 57344 | | Special values | NaN only | Inf and NaN | E4M3 uses 1 sign bit, 4 exponent bits, and 3 mantissa bits, with a bias of 7. E4M3 uses most bit patterns for normal finite numbers instead of saving many of them for special values. This helps E4M3 extend dynamic range, which is more useful for deep learning workloads. E5M2 uses 1 sign bit, 5 exponent bits, and 2 mantissa bits, with a bias of 15. E5M2 follows IEEE 754 conventions for the exponent field and special values, including infinities and NaNs. Because of this, it can be viewed as IEEE FP16 with fewer mantissa bits, like how bfloat16 and TF32 can be viewed as IEEE FP32 with fewer bits. This makes conversion between E5M2 and IEEE FP16 straightforward, while still providing a wider dynamic range than E4M3 When hardware executes an FP8 instruction, it must know the format of each source operand, the format of the destination result, and the scale factors to apply. Because FP8 modes can change per tensor, software may need to update the format and scaling settings frequently inside performance-critical code. For this reason, Arm introduced a dedicated control register - FPMR. FPMR is separate from FPCR. Hardware can recognize and rename FPMR writes more efficiently, making per-tensor FP8 mode changes closer to a normal register write rather than a pipeline-serializing control update. FPMR contains the following fields: | Field | Bits | Description | | F8S1 | [2:0] | Format of 1st FP8 source. 0b000 = E5M2, 0b001 = E4M3. | | F8S2 | [5:3] | Format of 2nd FP8 source. Same encoding as F8S1. | | F8D | [8:6] | Destination result Format for instructions that convert other floating-point formats to FP8. Same encoding as F8S1. | | OSM | [14] | Overflow Saturation for FP8 multiplication instructions. | | OSC | [15] | Overflow Saturation for FP8 convert instructions. | | LSCALE | [22:16] | Unsigned Log2 down-scaling factor. Result x 2^(−LSCALE). | | NSCALE | [31:24] | Unsigned Log2 up-scaling factor for widening FP8 sources. | | LSCALE2 | [37:32] | Second down-scaling value for dual-source convert instructions. | FP8 instruction set on Arm. The 2023 and 2024 architecture extensions add FP8 instructions across Advanced SIMD, SVE and SME. The following table summarizes the architectural features and the instructions they provide. | Architectural features | Supported category | Instructions | Description | | FEAT_FP8 | Advanced SIMD/SVE/SME | FCVTN, FCVT, F1CVT, F2CVT, BF1CVT, BF2CVT, FSCALE | FP8 convert instructions; a floating-point scale instruction. | | FEAT_FP8FMA | Advanced SIMD/SVE | FMLALB, FMLALT, FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT | FP8 widening multiply-accumulate. | | FEAT_FP8DOT4 | Advanced SIMD/SVE | FDOT (.S) | FP8 | FP32 4-way dot product. | | FEAT_FP8DOT2 | Advanced SIMD/SVE | FDOT (.H) | FP8 | FP16 2-way dot product. | | FEAT_SSVE_FP8FMA | SME | FMLALB, FMLALT, FMLALLBB, FMLALLTT | FP8 widening multiply-accumulate in Streaming SVE mode. | | FEAT_SSVE_FP8DOT4 | SME | FDOT (.S) | FP8 | FP32 4-way dot product and accumulate in Streaming SVE mode. | | FEAT_SSVE_FP8DOT2 | SME | FDOT (.H) | FP8 | FP16 2-way dot product and accumulate in Streaming SVE mode. | | FEAT_SME_F8F32 | SME | FMOPA, FDOT, FVDOTB, FVDOTT, FMLALL | FP8 outer product and accumulate into FP32 ZA tile; FP8 dot product and accumulate into FP32 ZA array; FP8 widening multiply-accumulate into FP32 ZA array; | | FEAT_SME_F8F16 | SME | FMOPA, FDOT, FVDOT, FMLAL | FP8 outer product and accumulate into FP16 ZA tile; FP8 dot product and accumulate into FP16 ZA array; FP8 widening multiply-accumulate into FP16 ZA array. | | FEAT_F8F32MM | Advanced SIMD/SVE | FMMLA | FP8 matrix multiply-accumulate to FP32 | | FEAT_F8F16MM | Advanced SIMD/SVE | FMMLA | FP8 matrix multiply-accumulate to FP16 | All FP8 compute instructions read the source format from FPMR (F8S1/F8S2) and apply scaling via LSCALE/NSCALE. These widening instructions always use FP8 data as the input format. Accumulation uses a wider type, such as FP16 or FP32. This keeps the bandwidth advantage of FP8 inputs while preserving numerical stability during accumulation. Further reading. For more detailed information about FP8, see the Arm Architecture Reference Manual for A-profile architecture and the FP8 Formats for Deep Learning paper. Part 2 will explore FP8 instructions, from conversion and scaling to dot products, matrix multiplication, and outer products in Advanced SIMD, SVE, and SME. Siyu Mou. Siyu Mou is an Arm engineer.

Arm's Q2 FY2027 revenue rose 27% as GAAP income fell. Arm reported $1.443 billion in fiscal Q2 revenue as licensing outpaced royalties; its AGI CPU revenue outlook spans fiscal 2027 and 2028. November 7, 2026 Key points * 01 Arm's reported fiscal Q2 FY2027 revenue was $1.443 billion, up 27% year over year. * 02 License and other revenue grew 50%; royalty revenue grew 8%. * 03 GAAP net income fell 45%, while non-GAAP net income rose 36%. * 04 The AGI CPU outlook covers fiscal 2027 and 2028 combined; fiscal Q3 guidance called for $1.54 billion in revenue, plus or minus $50 million. Arm's fiscal Q2 FY2027 revenue rose 27%, while GAAP net income fell 45%. Licensing outpaced royalties, and the AGI CPU outlook covers FY2027 and FY2028. Arm announced on November 4, 2026, that it had published its shareholder letter for fiscal Q2 FY2027, which ended September 30. The quarter's reported revenue rose 27% year over year to $1.443 billion, while GAAP net income fell 45%. The detailed financial figures come from 10jqka's results report and a GuruFocus earnings-call summary syndicated by Yahoo Finance. Arm's announcement gives the reporting period and letter-publication date. Licensing grew faster than royalties. Licensing and other revenue rose 50% to $773 million, while royalty revenue increased 8% to $670 million. That makes the difference in growth rates clear: licensing expanded much faster than royalties in the reported quarter. | Measure | Reported figure | Period or comparison | | Total revenue | $1.443 billion | Fiscal Q2 FY2027; up 27% year over year | | License and other revenue | $773 million | Fiscal Q2 FY2027; up 50% year over year | | Royalty revenue | $670 million | Fiscal Q2 FY2027; up 8% year over year | | GAAP net income | $130 million | Fiscal Q2 FY2027; down 45% year over year | | Non-GAAP net income | $566 million | Fiscal Q2 FY2027; up 36% year over year | | Non-GAAP diluted EPS | $0.52 | Fiscal Q2 FY2027; up 33% year over year | | Revenue guidance | $1.54 billion +/- $50 million | Fiscal Q3 FY2027 | | Non-GAAP operating expenses | About $825 million | Fiscal Q3 FY2027 guidance | | Non-GAAP diluted EPS guidance | $0.56 +/- $0.04 | Fiscal Q3 FY2027 | GAAP and non-GAAP income moved in opposite directions. GAAP net income was reported at $130 million, down 45% year over year; non-GAAP net income was $566 million, up 36%. These are separate accounting measures, so their different movements should be considered on their respective bases. In discussing the GAAP comparison, 10jqka cited a $46.6 million fair-value loss on listed equity investments and a $4.9 million expected credit loss related to Arm China. The year-earlier comparison included a $131 million pretax gain from the sale of the Artisan foundational IP business to Cadence. These were among the items identified in the reported comparison. 10jqka's account also gives the quarter's GAAP and non-GAAP figures. Data-center growth and the AGI CPU outlook. Arm's data-center royalties doubled year over year, while physical-AI royalties rose 50%, according to the two earnings reports. Arm's architecture accounted for more than half of server shipments at leading hyperscalers in calendar 2025, up from 15% in 2024; Arm forecast that share would exceed 60% by the end of calendar 2026. 10jqka and the GuruFocus summary reported these figures. Arm's AGI CPU outlook is for up to $2 billion in revenue across fiscal 2027 and fiscal 2028 combined. The first commercial deliveries were expected in fiscal Q4 FY2027. The two-year figure is an outlook, separate from the $1.443 billion reported for fiscal Q2. Keep the AGI CPU's $2 billion figure in the two-year outlook column; it is not revenue reported for the quarter. Arm's fiscal Q3 FY2027 guidance. Arm's reported guidance for fiscal Q3 FY2027 was revenue of $1.54 billion, plus or minus $50 million, and non-GAAP diluted earnings per share of $0.56, plus or minus $0.04. The earnings-call summary also put non-GAAP operating expenses at about $825 million. These are guidance figures for the next quarter, not Q2 results. Other Languages Read this article in another available language.

Arm Holdings shares fell about 13% on Thursday, November 5, after the British chip designer reported weaker smartphone royalties, hurt by a memory chip shortage. Memory makers are shifting production to AI data center chips, which raises phone costs. Arm's fiscal second quarter revenue rose 27% to $1.44 billion, its best second quarter ever. Royalty revenue grew just 8% to $670 million, while data center royalties doubled from a year earlier. IDC projects the global smartphone market will shrink 12.9% in 2026, the sharpest drop on record. Arm expects its first commercial deliveries of its own server chip, the Arm AGI CPU, in the quarter ending March 2027. It guided fiscal third quarter revenue to $1.54 billion, plus or minus $50 million.