Cadence certifies AI-driven reference flows for Intel 18A-P and Intel 14A. Friday 31st July 2026 The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital and custom design enablement, advanced packaging support, and power delivery-optimized flows for AI, HPC, mobile, and future aerospace applications. Cadence's AI-driven digital and custom reference flows, tools, and solutions are now certified on Intel 18A-P and Intel 14A technologies, based on the latest Intel Foundry process design kits (PDKs). Building on the companies' recent expansion of design IP optimized for Intel 18A and 18A-P and their multi-year Design Technology Co-Optimization (DTCO) agreement targeting Intel 14A, this new certification provides customers with a signoff-ready path to deploy advanced AI, high performance computing (HPC), and mobile SoCs on Intel Foundry's leading-edge nodes. Cadence has worked closely with Intel Foundry to co-optimize tools, flows, and methodologies that fully leverage the innovations in Intel 18A, Intel 18A-P, and Intel 14A, including RibbonFET Gate-all-around transistors and advanced backside power delivery technologies such as PowerVia and PowerDirect. By tightly coupling process capabilities with Cadence's agentic AI-driven EDA portfolio and high-performance design IP, customers can achieve industry-leading power, performance, and area (PPA) while reducing design risk and time to market. The new certifications reinforce Cadence's participation in the Intel Foundry Accelerator Ecosystem Alliance programs, where Cadence is a founding member focused on delivering robust design enablement for Intel Foundry's advanced nodes and interoperable, scalable chiplet solutions. Together, Cadence and Intel Foundry are working to ensure that customers across AI factories, data centers, and mobile have access to signoff-ready flows, IP, and packaging technologies that accelerate innovation. "As designers look for new ways to differentiate their products in this exciting era of AI, Intel Foundry's collaboration with ecosystem partners such as Cadence will help our customers turn their most ambitious ideas into reality," said Shawn Han, senior vice president and general manager, Foundry Services, Intel Corporation. "Through co-optimized, certified design flows and silicon-validated IP, we give our customers greater confidence that they can design on next-generation Intel Foundry technologies to achieve their specific power, performance and efficiency targets." The certified digital and custom reference flows span the full Cadence portfolio of AI-driven implementation, verification, and signoff solutions, including synthesis, place-and-route, timing and power signoff, physical verification, reliability verification, and analog/custom design. These flows are tuned to the PDKs for Intel 18A-P and Intel 14A, enabling design teams to quickly adopt Intel Foundry's advanced nodes with flows jointly validated for manufacturability, reliability, and yield. As part of the collaboration, Cadence and Intel Foundry have also co-developed an advanced packaging reference design flow that supports Intel Foundry's Embedded Multi-die Interconnect Bridge (EMIB) and EMIB-T technologies. This workflow streamlines the integration of complex multi-chiplet architectures by eliminating data conversion steps, enabling concurrent design activities, and providing early thermal, signal integrity, and power integrity analysis across dies and packages. In addition, Cadence and Intel Foundry have validated IP test chips in silicon on Intel 18A using Cadence interface and memory IP, demonstrating robust interoperability between Cadence IP, AI-driven flows, and Intel Foundry's power delivery optimized process technologies. This silicon validation enables IP choice for customers across the various nodes offered by Intel Foundry. Featuring RibbonFET 2 and PowerDirect second-generation gate-all-around and backside power delivery technologies, Intel 14A is expected to deliver higher performance at the same power compared to Intel 18A, making it a compelling choice for next-generation AI accelerators, cloud and edge HPC, premium mobile applications, and over time, aerospace and government designs. "The next era of AI, HPC, mobile, and advanced systems innovation will be defined by how quickly customers can move from bold architectural ideas to reliable silicon," said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. "Our expanded collaboration with Intel Foundry brings together Cadence's AI-driven EDA portfolio, robust co-optimized certified flows and platform, silicon-validated IP, and advanced packaging flows with Intel's advanced process technologies, giving design teams a trusted, signoff-ready path to achieve their power, performance, and time-to-market goals on Intel 18A-P and Intel 14A." Cadence will showcase the certified Intel 18A-P and Intel 14A flows, DTCO methodologies, and advanced packaging solutions at the Design Automation Conference (DAC), with technical sessions and demos highlighting customer use cases across AI, HPC, and mobile markets. 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The autonomous chip-to-system engineer has arrived. How Cadence, in collaboration with NVIDIA, is building the industry's first silicon-to-system agentic AI engineering platform For decades, the semiconductor industry has tackled growing complexity the same way: add more engineers, throw more compute at the problem, and extend schedules. That approach worked when complexity increased incrementally. Today, it no longer scales. Design teams that once numbered in the dozens now span thousands of engineers. Verification requires billions of compute hours every year. What used to take days can now take weeks, and the gap between engineering ambition and available resources continues to widen. The industry is reaching a turning point. At DAC 2026, Cadence, in collaboration with NVIDIA, is advancing a fundamentally different way forward: autonomous AI agents that can understand design intent, reason through complex engineering challenges, and implement meaningful portions of the design process with minimal human intervention. From AI assistants to AI engineers. Generative AI showed that models can help engineers write code. The next step is far more significant: AI systems that can take ownership of engineering tasks, evaluate results, decide what to do next, and continuously drive toward closure. That evolution begins with NVIDIA Nemotron 3 Ultra. Nemotron 3 Ultra now leads among open models in agentic RTL coding on the Comprehensive Verilog Design Problems (CVDP) benchmark. Combined with the ACE-RTL agent developed by NVIDIA Research, it goes beyond code generation. It can reason about hardware architecture, iterate on its own outputs, and pursue functional correctness through autonomous problem-solving. Equally important, enterprises can customize and deploy the model with their own design data. Rather than relying on opaque cloud-based systems, engineering organizations can preserve data privacy, maintain control over IP, and embed decades of accumulated design expertise directly into their AI workflows. At DAC, NVIDIA is extending this foundation even further through new capabilities in the NVIDIA Agent Toolkit, providing the infrastructure on which Cadence AI Super Agents are built. ChipStack AI Super Agent: Autonomous verification at scale. The real breakthrough happens when these models are connected to trusted engineering tools and workflows. At Computex 2026, Cadence announced that the ChipStack AI Super Agent achieved Level-5 autonomy and will now support NVIDIA Nemotron 3 Ultra models secured by NVIDIA OpenShell(TM) runtime. For companies operating at NVIDIA's scale, verification represents one of the largest engineering investments. Thousands of engineers spend billions of compute hours every year validating increasingly complex designs. The ChipStack AI Super Agent changes that equation. Instead of manually driving each step of the verification process, engineers can direct autonomous agents that simultaneously implement hundreds of simulations using Cadence Xcelium Logic Simulation and Jasper Formal Verification. Work that traditionally required five weeks can now be completed in less than a day - delivering more than 40X faster RTL validation cycles. More importantly, the ChipStack AI Super Agent is not simply automating individual tasks. It continuously evaluates results, determines the next best action, and moves through the complete workflow - from specification understanding and RTL development to verification planning, formal analysis, simulation, debugging, and convergence. The engineer's role shifts from implementing tasks to supervising outcomes. This autonomy is possible because the agents are grounded in Cadence's signoff-accurate simulation technologies - the same proven engines used for production tapeouts. NVIDIA OpenShell provides the governance layer required for enterprise deployment, helping organizations maintain IP protection, security controls, and operational oversight. The result is AI that can participate in real engineering work, not just assist with it. Extending agentic AI beyond the chip. Modern innovation no longer stops at the silicon boundary. As AI infrastructure grows increasingly complex, challenges in advanced packaging, PCB design, thermal management, and system optimization have become just as critical as the chip itself. To address this broader problem, Cadence introduced the AuraStack AI Super Agent on Cadence Allegro AI Studio, the industry's first agentic AI platform focused on PCB and advanced packaging design. Built on NVIDIA Agent Toolkit and powered by NVIDIA Nemotron 3 Ultra, the AuraStack AI Super Agent coordinates specialized agents across planning, implementation, and multiphysics analysis. Accelerated by NVIDIA Blackwell architecture and CUDA-X libraries - including cuDSS running on the Cadence Millennium M2000 Supercomputer - it brings agentic AI to the full system design process. The impact is substantial: * Up to 15X faster design workflows * Up to 2X faster time to market * Up to 20X faster multiphysics performance across signal integrity, power integrity, electromagnetic, and thermal simulations Perhaps most importantly, the AuraStack AI Super Agent introduces a unified multiphysics environment where electrical, thermal, and mechanical interactions can be evaluated concurrently. Problems that would traditionally surface late in development can now be identified and resolved much earlier, reducing costly redesign cycles and accelerating system convergence. NVIDIA engineers are already using the AuraStack AI Super Agent to tackle some of the industry's most demanding AI infrastructure challenges. The first complete silicon-to-system agentic AI stack. With the introduction of the AuraStack AI Super Agent, Cadence has assembled the industry's most comprehensive portfolio of agentic AI solutions, spanning the entire electronic system design flow. Together, Cadence's AI Super Agents create an integrated autonomous engineering ecosystem powered by NVIDIA Nemotron 3 Ultra, Blackwell, and CUDA-X: * ChipStack AI Super Agent - Autonomous chip design and RTL verification * InnoStack AI Super Agent - Digital implementation and signoff * ViraStack AI Super Agent - Custom and analog design * AuraStack AI Super Agent - PCB and advanced packaging The combination of Cadence's engineering expertise and NVIDIA's AI platform is creating something neither company could deliver independently: a physics-accurate, governed, silicon-to-system agentic engineering stack capable of transforming how electronic systems are designed. Experience it at DAC 2026. DAC 2026 is where this vision becomes tangible. At the Cadence booth and throughout the conference, attendees will see autonomous verification workflows running live. A year ago, many of these workflows would have sounded aspirational. Today, they are real. The industry's conversation is no longer about whether AI can assist engineers. The question is how quickly autonomous engineering systems will become part of every design team's workflow. At DAC 2026, you'll see the answer firsthand: The autonomous engineer has arrived.

Cadence's Agentic AI Design Vision takes center stage at DAC. July 27, 2026 AI infrastructure demands are changing what semiconductor design must solve. The challenge is no longer only about creating faster silicon; it is about designing complete systems where silicon, advanced packaging, PCB, power delivery, thermal behavior, and mechanical reliability interact from the start. That system-level complexity is redefining AI's role in EDA. What began as AI-assisted automation is now advancing toward agentic AI - systems that can reason over objectives, navigate tradeoffs, orchestrate workflows, and help drive decisions across exploration, optimization, and convergence. That is the vision Cadence is bringing to this year's Design Automation Conference (DAC): helping design teams move from disconnected iteration to connected, agentic AI-driven design. Cadence Expands Agentic AI Across the Design Continuum The next era of AI infrastructure, spanning across applications such as data centers, automotive, and aerospace, will be defined not only by silicon but also by the systems that connect, power, and cool it. At DAC 2026, taking place in Long Beach, California, Cadence will highlight the Cadence AI stack spanning design, verification, implementation, packaging, and PCB. AI super agents orchestrate complex workflows while trusted technologies across these domains help engineering teams move from intent to realization more efficiently. Cadence will showcase extended agentic AI across the design continuum and how these capabilities come together in practical workflows for AI-era system design. What Cadence Will Showcase at DAC 2026 Cadence's DAC 2026 presence is best understood as a chip-to-final-product approach in a single AI-native environment. The expanding portfolio of Cadence AI Super Agents addresses different layers of engineering complexity while moving in one direction: from point automation toward coordinated intelligence across the full electronic design flow. The ChipStack AI Super Agent applies agentic AI to front-end silicon design and verification, supporting activities such as RTL generation, testbench creation, verification planning, regression orchestration, debugging, and issue resolution. It is designed to deliver up to 10X productivity improvements across key design and verification tasks. The ChipStack AI Super Agent is where Cadence's agentic AI vision meets NVIDIA Nemotron 3 Ultra, a leading, efficient open model for agentic RTL design and verification. Together, they help Cadence customers bring accurate, efficient, and customizable models into their workflows, with ChipStack coordinating specialized agents across RTL generation, testbench creation, regression orchestration, and debug. The ViraStack AI Super Agent extends agentic automation into custom and analog design, helping with schematic creation, circuit optimization, testbench development, and layout migration. The InnoStack AI Super Agent focuses on digital implementation and signoff - from synthesis and place-and-route through signoff analysis and ECO execution - using specialized agents to speed iteration and convergence. The newly announced AuraStack AI Super Agent extends agentic AI into PCB and advanced packaging. As AI systems continue to grow larger, more heterogeneous, and more power-intensive, engineering teams face increasing pressure to evaluate tradeoffs across multiple domains earlier in the design process. The unified, AI-driven multiphysics foundation in AuraStack AI Super Agent concurrently models and optimizes electrical, thermal, and mechanical behavior, as engineering success depends on understanding these interactions before they become costly problems. For DAC attendees, this is one of the most important proof points: Agentic AI is not only about automating tasks; it is about bringing system-level feedback into the design flow while teams still have room to act. EDA Tools Are Still an Important Piece of the Cake Behind every AI breakthrough lies a much larger technology stack that includes advanced computing infrastructure, physically accurate computational software, and intelligent automation working together. The intelligence of an agentic workflow is only as useful as the EDA tools backing it up. The important point for design teams is that agentic AI does not replace the EDA foundation. It depends on it. That is why Cadence's established EDA tools remain essential to chip and system design. Engineering design teams now can use agentic AI with proven engines for simulation, formal verification, synthesis, implementation, timing, power, signoff, analog optimization, PCB implementation, and multiphysics analysis. Why Accelerated Compute Matters Agentic AI workflows also require compute infrastructure capable of supporting large-scale simulation, optimization, and analysis at speed. That is where the Cadence - NVIDIA collaboration becomes an important part of the broader system-design message. Cadence and NVIDIA are working together to accelerate engineering solutions for AI chips and system design by combining Cadence AI-enabled solutions with NVIDIA accelerated computing technologies, including NVIDIA Grace CPUs, Blackwell GPUs, and CUDA-X libraries. In addition, NVIDIA is using Cadence solutions to help automate and optimize increasingly complex system design workflows for its engineering teams. The message is straightforward: Intelligent orchestration becomes more powerful when paired with accelerated computing. At DAC 2026, that connection helps demonstrate how Cadence is addressing both sides of the system-design challenge - the need to automate complex workflows and to run compute-intensive analysis efficiently. See Cadence's Agentic AI Design Vision at DAC 2026 At DAC 2026, Cadence will show how agentic AI, trusted design technologies, accelerated computing, and domain-specific expertise come together to help engineers tackle increasingly complex design, verification, implementation, packaging, and system-level challenges. Visit the Cadence DAC booth to explore its Agentic AI solutions across chip, package, and board design; see other exhibits on chiplets and accelerated verification; meet with its experts; and attend Cadence-led papers and panels throughout the conference.