Analog Devices buys Empower Semiconductor for $1.5B. 5:52 6 min SAN JOSE, California: Analog Devices said on May 19, 2026, that it will acquire Empower Semiconductor for roughly $1.5 billion in an all-cash transaction, expanding its push into the chips that feed AI accelerators. The deal was disclosed in an 8-K filing with the Securities and Exchange Commission and a joint press release from the two companies. Both boards have approved the deal, which is expected to close in the second half of calendar 2026 subject to Hart-Scott-Rodino antitrust review. Empower, based in Silicon Valley, builds integrated voltage regulators, known as IVRs, and silicon capacitors. Those chips sit physically next to GPUs and AI accelerators and handle the last stage of power delivery, converting and routing energy at the point of consumption. ADI is folding the technology into what it calls a grid-to-core power platform, a portfolio meant to cover everything from utility-scale conversion at the data center fence to power management on the silicon die itself. Why ADI is paying for power delivery. The acquisition is ADI's largest move into AI infrastructure to date and reflects a shift in where chipmakers see scarcity. Through 2024 and 2025, hyperscalers and the Magnificent Seven competed primarily on GPU supply. By early 2026, the binding constraint had moved downstream. Power density, not raw wattage, became the limit on how much compute can be packed into a single rack. "AI infrastructure is fundamentally reshaping how power must be delivered, with energy now the most persistent constraint to scaling next-generation systems," ADI chair and chief executive Vincent Roche said in the company's announcement. Roche framed the deal as a way to help customers "rearchitect their power systems and achieve the compute densities next-generation AI demands," and noted the technology applies "well beyond AI data centers to any domain where energy constrains what is possible." Empower has been moving in that direction commercially. Earlier this year the company announced a collaboration with Marvell Technology to develop integrated power solutions for Marvell's custom silicon platforms, the kind of accelerator chip that hyperscalers are designing in-house for AI workloads. Empower's flagship Crescendo IVR series is engineered to be roughly five times smaller than traditional board-level designs, with faster transient response and higher efficiency, according to Empower's product documentation. What does the ADI Empower acquisition mean for AI infrastructure? The deal signals that AI capital is now flowing downstream from GPUs into the picks-and-shovels layer beneath them. Power delivery, cooling, and on-die conversion are emerging as the new bottlenecks for hyperscalers, and ADI is paying a premium to own that layer rather than license it. Founders in adjacent categories should expect more strategic M&A on the power-electronics side over the next 12 months. Empower chief executive Tim Phillips described the company's mission as solving "the hardest problem in AI power delivery." That framing now becomes ADI's positioning. The combined entity will own intellectual property across the full power path, which matters because hyperscalers increasingly buy power architecture as a system, not as discrete components. Marvell, Nvidia, and the in-house silicon teams at Amazon, Google, and Microsoft each design their accelerators around assumptions about how power will reach the die. ADI is now selling into that conversation with a single integrated stack. The financial structure also says something about ADI's confidence. An all-cash $1.5 billion deal from a company with a market capitalization north of $110 billion is not a financing stretch, but it is a clear capital allocation choice. ADI is funding it from cash on hand rather than issuing stock, which suggests management views Empower's pipeline as a near-term contributor to revenue rather than a speculative bet. What founders should watch next. The first signal to track is regulatory. The Hart-Scott-Rodino waiting period will run through the summer, and antitrust enforcement of vertical chip acquisitions has tightened since the Justice Department's review of recent semiconductor deals. ADI's filing language emphasizes "customary closing conditions," but a second request from the Federal Trade Commission would push the close into late 2026 or early 2027. The second signal is competitive response. Texas Instruments, Infineon, and STMicroelectronics all compete with ADI in power-management chips and have not yet made a comparable bet on integrated voltage regulators. Whether any of them moves on Empower's smaller competitors, including Vicor and ferroelectric-capacitor specialists, will indicate how quickly the rest of the power-electronics market follows ADI into AI-specific architectures. The third signal is adjacent. ADI's deal lands two weeks after Cowboy Space raised $275 million to build orbital data centers and one week after Kevin O'Leary's nine-gigawatt Stratos project drew renewed scrutiny. Each of those bets reflects the same underlying thesis. The AI buildout has shifted from "we need more chips" to "we need to get power to the chips we already have." Expect the M&A flow, the venture capital, and the policy attention to track that shift over the rest of 2026.

Google partners with Marvell on new AI chips to challenge Nvidia. The partnership. Alphabet Inc.'s Google is currently in talks with Marvell Technology to develop two new chips aimed at running AI models more efficiently. This collaboration, reported by The Information on Sunday citing two people with knowledge of the discussions, marks a strategic shift in how the tech giant approaches its hardware infrastructure. Google has long relied on internal custom silicon, but external partnerships are becoming increasingly common as the demand for AI compute scales beyond what internal labs can easily manage. The partnership is not merely about securing manufacturing capacity. It is a direct effort to improve performance metrics that define the modern AI landscape. Efficiency is the metric that matters now. Training and inference models consume massive amounts of power and memory bandwidth. By integrating Marvell's expertise, Google aims to address these bottlenecks before they become critical failures in production environments. The companies aim to finalize the design of the memory processing unit as soon as next year before handing it off for test production. While Reuters could not immediately verify the report, the context suggests a necessary evolution. Google faces a crowded market where hardware compatibility often dictates software deployment. If Google's Tensor Processing Units (TPUs) remain proprietary, adoption is limited to Google Cloud customers. If these new chips can run on broader hardware stacks, they could expand the addressable market for Google's infrastructure services. The report indicates the companies are focused on efficiency. In high-compute environments, efficiency directly translates to cost savings. For cloud providers, every watt of power consumed during inference reduces the margin available for growth. Hardware strategy. One chip is a memory processing unit designed to work with Google's tensor processing unit (TPU), and the other chip is a new TPU built specifically for running AI models. This distinction is vital for understanding Google's hardware roadmap. The memory processing unit addresses a specific weakness in current architectures. AI models often starve for data movement rather than raw compute power. Memory bandwidth is the primary constraint in modern large language model inference. The second chip, a new TPU, represents a direct competitor to Nvidia's dominant GPUs. Nvidia currently controls the vast majority of the market for AI training and inference. Google has been pushing to make its TPUs a viable alternative to Nvidia's GPUs. This is not a secondary goal. TPU sales have become a key driver of growth in Google's cloud revenue. The company needs to diversify its revenue streams beyond general-purpose computing. The architecture of these new chips matters. Nvidia's GPUs rely on CUDA, a proprietary software stack that developers have built over decades. Google's TPUs rely on JAX and other frameworks. By developing a new TPU specifically for running AI models, Google is attempting to bridge the gap between software frameworks and hardware acceleration. If the new TPU can match Nvidia's performance-per-watt while running on a compatible software stack, it could disrupt the current ecosystem. However, the strategy requires balancing performance with compatibility. Developers prefer hardware that supports their existing workflows. If the new TPU requires significant code rewriting, adoption will be slow. The memory processing unit helps here by optimizing data transfer between the memory and the compute core. This reduces latency without increasing clock speeds. In practical terms, this means faster model loading times and reduced inference costs for enterprise customers. The financial stakes are high. Nvidia's dominance is built on a moat of software and hardware integration. Google cannot simply match Nvidia's raw compute power. It must offer better economics. The new chips aim to run AI models more efficiently. Efficiency implies lower operating costs for data centers. For Google, this means higher margins on cloud infrastructure sales. For customers, it means lower bills for running large language models. Financial goals. TPU sales have become a key driver of growth in Google's cloud revenue as the company aims to show investors that its AI investments are generating returns. This is the primary motivation behind the partnership. Investors scrutinize capital expenditure on hardware. If Google spends billions on custom silicon but cannot sell the hardware effectively, returns on investment suffer. The new partnership with Marvell provides a pathway to externalize these assets. Google's internal TPU usage is well documented. It powers the search engine and the recommendation systems that drive ad revenue. Now, the goal is to monetize that silicon outside of Google Cloud's internal use. Selling TPUs to third-party enterprises is difficult. Most enterprises rely on Nvidia GPUs because the software ecosystem is mature. Google needs to change that perception. The new TPU built specifically for running AI models is designed to compete with Nvidia's dominant GPUs. Competition forces innovation. If Google can offer a product that is cheaper or faster than Nvidia's offering, it will capture market share. This is not about beating Nvidia in a single benchmark. It is about winning the customer base. Large enterprises are looking for alternatives to Nvidia to avoid vendor lock-in. Google's entry into this space provides that option. Revenue growth is tied to hardware sales. If TPU sales grow, Google can justify further investment in AI research. This creates a virtuous cycle. Revenue funds research, which improves hardware, which generates more revenue. The partnership with Marvell accelerates this cycle. Marvell brings established manufacturing relationships. This reduces the risk of production delays. Production delays cost money in downtime and lost sales. The companies aim to finalize the design of the memory processing unit as soon as next year. This timeline suggests urgency. Google's cloud division is under pressure to grow. Hardware sales are a way to accelerate that growth. Investors want to see revenue diversification. If cloud revenue relies solely on compute power, it is vulnerable to cyclical downturns. Selling specialized hardware like TPUs provides a more stable revenue stream. Google and Marvell did not immediately respond to a request for comment. This is standard for the industry. Companies rarely comment on early-stage negotiations. However, the leak itself confirms the direction of the partnership. Analysts have noted that Google needs to improve its hardware margins. If the TPU can be sold at a profit, it changes the financial equation for the entire company. Development timeline. The companies aim to finalize the design of the memory processing unit as soon as next year before handing it off for test production. This schedule is aggressive but realistic for a collaboration of this size. Google has a long history of internal chip design. Marvell has a long history of external chip design. Combining these capabilities reduces the learning curve. Test production is the next step. This involves manufacturing small batches to validate yield and performance. Yield rates are critical. If the new chips have a high defect rate, they will be unsellable. Google's internal use of TPUs is forgiving. A production chip must be flawless for external customers. The design finalization precedes handing off for test production. This sequence ensures that the architecture is stable before silicon fabrication begins. Reuters could not immediately verify the report. Verification is difficult in the semiconductor industry. Supply chain details are often confidential. However, the timing aligns with Google's broader strategy. The company has been reducing its reliance on Nvidia GPUs for internal tasks. The new chips are the culmination of that work. If the partnership fails, Google can still rely on internal design. If it succeeds, it opens new revenue channels. Google and Marvell did not immediately respond to a request for comment. This lack of comment does not negate the report. It simply means the companies are in the early stages of disclosure. In the tech industry, leaks often precede official announcements by weeks or months. The design timeline is public knowledge in the industry. The specific partnership is the variable. This partnership signals a shift in the AI hardware market. Nvidia's dominance is being challenged not just by new players, but by established ones like Google. The focus on efficiency and revenue generation indicates a mature understanding of the market. The new chips are not just faster processors. They are economic tools. By reducing the cost of running AI models, they make AI accessible to more applications. The design finalization precedes handing off for test production, ensuring a path to market. This is a significant development for the industry.