NXP launches MCX A5 MCUs with 10BASE-T1S PHY and post-quantum security. August 19, 2026 / SemiMedia / - NXP Semiconductors has introduced the MCX A5 family of microcontrollers, combining Ethernet connectivity and post-quantum security for industrial and IoT edge applications. According to NXP, the MCX A5 is the industry's first wired MCU implementation to combine topology discovery with an integrated 10BASE-T1S Ethernet digital PHY. The architecture allows more distributed industrial nodes to connect to Ethernet while reducing the component count, cost and complexity associated with conventional industrial networking. The MCX A5 family is based on an Arm Cortex-M33 core operating at up to 240 MHz. Its integrated 10BASE-T1S digital PHY supports compact, low-cost multidrop Ethernet networks for industrial automation, building control, energy infrastructure and other distributed edge applications. When paired with NXP's TJF1410 10BASE-T1S Physical Medium Dependent transceiver, the MCX A5 provides a complete single-pair Ethernet solution. The TJF1410 serves as the analog front end for the MCU's integrated digital PHY and supports IEEE 802.3cg-compliant 10BASE-T1S networks. The family combines PSA Certified Level 3 security with post-quantum cryptography support. Security capabilities include a PQC-based hardware root of trust, secure boot, secure firmware updates, secure attestation and secure debug authentication. Selected MCX A5 devices also support the Rust programming language, allowing developers to use memory-safe software development practices in products with extended operating lifecycles. MCX A5 devices offer up to 2 MB of Flash memory and 640 KB of RAM. Available interfaces include UART, I[2]C, I3C, SPI, CAN FD, High-Speed USB and FlexIO. Development support includes the MCUXpresso SDK, Long Term Support software releases, Visual Studio Code integration, NXP FRDM development boards and Zephyr RTOS. NXP said the software and security framework is intended to support long-term maintenance and evolving cybersecurity requirements, including those introduced by the European Cyber Resilience Act. The MCX A5 family is sampling now. Analog Devices plans new price adjustment effective September 13 AI server demand lifts top five NAND Flash suppliers' revenue 77% in 2Q26 All comments (0). No Comment.

Edge AI must be designed for trust, latency & power, says NXP's Hitesh Garg. Speaking at the ETElectronicsWorld Design & Verification Summit 2026 in Bengaluru, Hitesh Garg, Vice President & India Country Manager, NXP Semiconductors, said the shift from cloud AI to physical and edge AI will require architectures that combine ultra-low latency, power efficiency and security by design. * Updated On Aug 18, 2026 at 11:59 AM IST * * Copy Link * Share on WhatsApp * Share on Linkedin * Share on X * Share on Telegram * Share on Facebook BENGALURU: As artificial intelligence moves from the cloud into robots, vehicles, drones and industrial systems, trust, latency and power efficiency will become non-negotiable design requirements, according to Hitesh Garg, vice president & India country manager, NXP Semiconductors. Delivering an industry address at the ETElectronicsWorld Design & Verification Summit 2026 in Bengaluru, Garg said the industry is entering an era in which intelligence increasingly needs to operate at the edge, particularly as machines begin interacting directly with the physical world. "We are moving from AI on the cloud to AI on the edge," he said, arguing that the transition will demand a rethink of how intelligent systems are architected. The difficulty, Garg noted, is that many tasks humans perform instinctively - walking, maintaining balance, handling objects or reacting to sudden movement - remain highly complex for machines. As robotics, software-defined vehicles, autonomous mobile robots and drones evolve, engineers will need to recreate such real-time responses within constrained computing and power environments. Bringing human-like reflexes to machines Garg drew inspiration from the way the human nervous system distributes intelligence. He described a three-layer architecture consisting of a reasoning layer for higher-level decision-making, a coordination layer for managing different functions, and a reflexive layer capable of responding almost instantaneously without waiting for central processing. In an autonomous system such as a drone, for instance, central computing can handle planning, while another layer coordinates the system and local controllers manage individual motors and immediate responses. Such distributed architectures can help reduce dependence on a single processing point while improving response time and power efficiency. For real-world intelligent systems, Garg identified three critical requirements: ultra-low latency responses, distributed control and power efficiency. The approach, he said, can extend across applications ranging from drones and autonomous mobile robots to automotive, aerospace and industrial systems. Trust cannot be added later But faster edge intelligence alone will not be sufficient. "Trust in human beings, we kind of build the trust. For machines, they have to be designed," Garg said. As intelligent machines take on greater responsibility, failures can have consequences beyond software errors. Industrial accidents, compromised autonomous systems or vulnerabilities in connected equipment make safety and security fundamental architecture considerations. Garg outlined several layers required to establish that trust. The first is functional safety and redundancy, allowing another part of the system to take over when a component fails. The second is scalable hardware security, including the ability to prepare systems for emerging threats such as quantum computing. He also highlighted the need to secure AI itself as it becomes embedded in more devices and applications. Verification forms another critical layer. Rather than treating it simply as certification at the end of development, Garg said it should be incorporated into the design process and test whether chips and systems continue to operate reliably across different temperatures and operating conditions. Hardware must remain secure for years The challenge becomes particularly significant for products expected to remain deployed for a decade or longer. Automotive and industrial hardware designed today may still be operating 10 to 15 years from now, even as cybersecurity threats continue to change. Garg said systems therefore need mechanisms such as secure lifecycle updates and "crypto agility" so that protection can evolve after hardware has entered the field. "How do we make ourselves future-proof?" he said, framing it as a fundamental requirement for engineers designing long-life systems. That ability to adapt becomes increasingly important as AI migrates into devices whose physical actions cannot simply be reversed. "Real life has no undo button," Garg said. If an intelligent machine makes the wrong physical decision, a subsequent software update cannot reverse the consequences. Edge AI needs a different design mindset The shift towards physical AI therefore changes both where intelligence resides and how semiconductor systems must be designed. Cloud computing will continue to play a role, but applications requiring immediate reactions increasingly need inference and control closer to where data is generated and actions are taken. For semiconductor companies, that means delivering enough intelligence at the edge while simultaneously managing tight power budgets, latency requirements, functional safety and cybersecurity. Garg said these requirements need to be considered together rather than solved independently. Distributed, biologically inspired architectures provide one way to balance the competing demands, but trust must remain embedded throughout the system. As AI moves from generating digital outputs to controlling machines in factories, vehicles and other physical environments, Garg's central argument was that computing capability alone will not determine adoption. The systems that succeed will be those designed from the outset to respond quickly, operate efficiently and remain trustworthy throughout their working life. * Published On Aug 18, 2026 at 11:59 AM IST

Nokia is expanding its US optical manufacturing capabilities with a multi-state strategy. The company is opening a new optical components plant in San Jose, California, scheduled to begin production in Q4 2026. It is also increasing its Pennsylvania facility's testing and packaging capacity tenfold, with the first phase launching in Q3 2026. Additionally, Nokia has reached a final agreement to acquire NXP Semiconductors' fabrication campus in Chandler, Arizona. The company will lease and begin converting part of the facility in early 2027 to manufacture Indium Phosphide semiconductors, which are critical for high-speed optical devices used in AI data centres. Nokia will complete the acquisition in Q1 2029. The expansion aims to create a domestic US supply chain for optical components amid surging demand from AI infrastructure development.