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Full-Time

Design Verification Engineer

Staff

Posted on 6/18/2024

d-Matrix

d-Matrix

51-200 employees

AI compute platform using in-memory computing

AI & Machine Learning
Data & Analytics
Hardware

Senior

Santa Clara, CA, USA

Category
QA & Testing
Quality Assurance
Requirements
  • MS in EE or CS
  • 5+ years industry experience
  • Experience in SoC verification cycle
  • Good knowledge of verification methodologies such as UVM/OVM
  • Hands-on ASIC-SoC Design verification tests and debug experience
  • Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology
  • Good problem-solving skills
  • Passion for challenges in AI domain
  • Experience with SystemVerilog and verification methodology (UVM/OVM/VMM)
  • Passionate about AI
  • Experience with C/C++ and SystemC (preferred)
  • Successfully led creation/implementation of multiple SoC verification environments and tape out efforts
Responsibilities
  • Work on a path-breaking architecture with a highly experienced team
  • Contribute to building a successful business
  • Express oneself and become a future leader in the industry
  • Strive to build a culture of transparency, inclusiveness, and intellectual honesty
  • Always learning and having fun on the journey

d-Matrix is developing a unique AI compute platform using in-memory computing (IMC) techniques with chiplet level scale-out interconnects, revolutionizing datacenter AI inferencing. Their innovative circuit techniques, ML tools, software, and algorithms have successfully addressed the memory-compute integration problem, enhancing AI compute efficiency.

Company Stage

Series B

Total Funding

$161.5M

Headquarters

Santa Clara, California

Founded

2019

Growth & Insights
Headcount

6 month growth

0%

1 year growth

20%

2 year growth

127%