Senior CPU RTL Front End Designer

• Contribute to CPU frontend designs, with emphasis on microarchitecture and RTL design for the next generation CPU.
• Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture enhancements. Facilitate final decision making.
• Deliver designs meet Power, performance and area (PPA) goals with production quality.
• Become familiar with techniques for at least one processor functional block. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA; Poughkeepsie, NY, USA.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.