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Soc Design Engineer
Posted on 8/20/2022
INACTIVE
Locations
Vancouver, BC, Canada
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
C/C++/C#
Java
Linux/Unix
Perl
Python
Verilog
Requirements
  • Bachelor or Master's Degree in Electrical Engineering, Computer Engineering, or other related fields
  • Familiar with RTL design and verification flow such as lint and code coverage
  • Hands-on experience in at least one scripting language (Perl, Tcl, Python etc.)
  • Logic Design, Simulation and Debugging
  • Verilog/System Verilog coding
  • Synthesis using Design Compiler or equivalent
  • Verification Methodology/UVM a plus
  • Good team player with strong communication skills
Desired Qualifications
  • FPGA design, debug and development experience is a plus
  • Error Correction Code background is a plus
Solidigm

1,001-5,000 employees

SSD storage solutions
Company mission
Solidignm's mission is to break the barriers blocking advancements in storage technology that are critical to unlocking data's unlimited potential. By reinventing how data is stored, accessed, and put to work in new ways, they empower their customers and unlock data's ability to do good.
Company Values
  • Customer-inspired - We listen and understand our customers' business and technology challenges, anticipating their needs and partnering to solve problems together.
  • Invention - We're passionate inventors and technologists that partner to unlock the power of data to solve the world's greatest challenges and fuel human advancement.
  • Excellence - We're committed to producing quality and responsible technologies and solutions with tenacity and integrity, demonstrating unparalleled discipline and expertise.
  • Partnership - We prioritize relationships with our teammates, customers, partners, and communities, exhibiting trust and mutual respect.
  • Openness - We treat people equitably and with respect, valuing different perspectives and new ideas.