Principal Engineer
Post-Silicon Bring-up / Validation : Ethernet Physical Layer
Posted on 7/19/2023
INACTIVE
SambaNova Systems

51-200 employees

Hardware for AI
Company Overview
SambaNova's mission is to enable the future of AI today by providing purpose-built deep learning solutions, delivered as a service and deployable in weeks rather than years to accelerate AI adoption and value creation.
AI & Machine Learning
Financial Services
Government & Public Sector

Company Stage

Series D

Total Funding

$1.1B

Founded

2017

Headquarters

Palo Alto, California

Growth & Insights
Headcount

6 month growth

-52%

1 year growth

-9%

2 year growth

-3%
Locations
Palo Alto, CA, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
Bash
Python
CategoriesNew
Software Engineering
Requirements
  • BS or MS degree in EE, ECE or CS
  • 5+ years of practical experience in silicon/system bring-up and debug
  • Demonstrated experience with high-speed Ethernet subsystem bring-up [minimum 56G PAM4, 100G/200G ports]
  • Understanding of embedded/system FW and PHY drivers for triage and diagnostic tooling
  • Excellent debugging skills at both SoC and system level
  • Strong programming and scripting skills (C/C++, Python, bash, etc.)
  • Self-starter and ability to drive tasks to completion with minimal guidance
Responsibilities
  • Develop and execute post-silicon bring-up and validation plan (characterization, stress test, functional and performance validation) for Ethernet physical layer(L1) in the SambaNova DataScale® system
  • Provide leadership and domain expertise for Ethernet physical layer up to 100G PAM4, 400/800G ports , FEC, MAC/PCS
  • Perform system-level debug and root-cause analysis through bring-up, validation, and production phase
  • Partner with system, product, and software teams on product test deployment, RMA debug, and product release
  • Collaborate with design, verification/emulation and software to ensure bring-up readiness (e.g. power-on sequence, debug tool and script, contingency planning)
  • Engage in pre-silicon verification, emulation and software development effort related to Ethernet L1 layer
  • Drive technical innovation in post-silicon infrastructure including tools and script development, technical and procedural methodology enhancement, and ongoing monitoring and other cross-functional technical initiatives
Desired Qualifications
  • Familiarity with pre-silicon validation/emulation
  • Ability to isolate/triage electrical vs functional issues
  • Working knowledge of Ethernet architecture (MAC/PCS/FEC) and experience engaging with architects and vendors on these issues