d-Matrix has fundamentally changed the physics of memory-compute integration with our digital in-memory compute (DIMC) engine. The “holy grail” of AI compute has been to break through the memory wall to minimize data movements. We’ve achieved this with a first-of-its-kind DIMC engine. Having secured over $154M, $110M in our Series B offering, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with our chiplets and In-Memory compute approach. We are on track to deliver our first commercial product in 2024. We are poised to meet the energy and performance demands of these Large Language Models.The company has 100+ employees across Silicon Valley, Sydney and Bengaluru.
Our pedigree comes from companies like Microsoft, Broadcom, Inphi, Intel, Texas Instruments, Lucent, MIPS and Wave Computing. Our past successes include building chips for all the cloud hyperscalers globally - Amazon, Facebook, Google, Microsoft, Alibaba, Tencent along with enterprise and mobile operators like China Mobile, Cisco, Nokia, Ciena, Reliance Jio, Verizon, AT&AT. We are recognized leaders in the mixed signal, DSP connectivity space, now applying our skills to next generation AI.
Location:
Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week.
The role: Physical Design Engineer, Senior Staff
The candidate will be responsible for the 7nm high speed physical designs and working with a 3rd party design services to implement and verify.
What you will do:
Methodology & Flow development of Physical Design and Timing Closure for custom and semi-custom blocks.
Floorplanning including multi-power domain, PG planning etc.
Physical implementation of blocks and top-level including clock-tree.
Physical verification, Timing closure and Formal verification for blocks and top-level.
Static and dynamic IR drop analysis, signal, and power EM checks.
Interfacing with internal and external teams including Design, IP, Library.
Interfacing with 3rd party Design Services company to ensure physical design achieves the best QoR.
What you will bring:
Minimum:
MS in EE/CS with 8-10 years of previous experience.
Exposure on ASIC design, layout and semiconductor device/process through previous work/intern experience or course work.
Experience with scripting/programming using Tcl/Tk/Perl.
Detail oriented, self-motivated team worker, good verbal and written communication skills.
Previous experience on physical design and automatic place and route a plus. i.e., Knowledge of Synopsys/Cadence P&R tools.
Preferred:
#LI-BP1
Equal Opportunity Employment Policy
d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.
d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.
