Full-Time

Physical Design Engineer – Senior Staff

Posted on 4/5/2024

d-Matrix

d-Matrix

51-200 employees

AI compute platform using in-memory computing

AI & Machine Learning
Data & Analytics
Hardware

Senior

Santa Clara, CA, USA

Required Skills
Perl
Requirements
  • MS in EE/CS with 8-10 years of previous experience
  • Exposure on ASIC design, layout, and semiconductor device/process
  • Experience with scripting/programming using Tcl/Tk/Perl
  • Detail-oriented, self-motivated team worker, good verbal and written communication skills
  • Previous experience on physical design and automatic place and route
  • Knowledge of Synopsys/Cadence P&R tools
  • Experience on custom layout and physical verification
  • Experience on synthesis/STA/FV
Responsibilities
  • Methodology & Flow development of Physical Design and Timing Closure for custom and semi-custom blocks
  • Floorplanning including multi-power domain, PG planning etc.
  • Physical implementation of blocks and top-level including clock-tree
  • Physical verification, Timing closure, and Formal verification for blocks and top-level
  • Static and dynamic IR drop analysis, signal, and power EM checks
  • Interfacing with internal and external teams including Design, IP, Library
  • Interfacing with 3rd party Design Services company to ensure physical design achieves the best QoR

d-Matrix is developing a unique AI compute platform using in-memory computing (IMC) techniques with chiplet level scale-out interconnects, revolutionizing datacenter AI inferencing. Their innovative circuit techniques, ML tools, software, and algorithms have successfully addressed the memory-compute integration problem, enhancing AI compute efficiency.

Company Stage

Series B

Total Funding

$161.5M

Headquarters

Santa Clara, California

Founded

2019

Growth & Insights
Headcount

6 month growth

0%

1 year growth

28%

2 year growth

203%
INACTIVE