SOC Physical Design STA/Timing Engineer
Confirmed live in the last 24 hours
Mountain View, CA, USA
- Bachelor's degree in electrical engineering, computer engineering or computer science
- Experience in static timing analysis and timing closure of high-performance SOC designs
- Full chip and block level STA tapeout experience, constraint generation and partitioning
- Knowledge of deep sub-micron FinFET technology nodes (7nm and below) timing challenges, multi-corner and multimode timing closure, process variations, voltage drop aware STA, and clock reconvergence pessimism removal
- Experience in IP integration (e.g. memories, I/Os, Analog IPs, SerDes, DDR etc.)
- Experience in industry standard STA and Noise/Signal integrity analysis tools
- Experience in clock jitter simulation and analysis methodologies
- Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on physical design and timing closure
- Deep understanding of ASIC synthesis and physical design flows and methodologies
- Experience with high reliability design and implementations
- Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile, etc.)
- Familiar with implementation or integration of design blocks using Verilog/System Verilog
- Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
- Must be willing to travel when needed (typically <10%)
- Willing to work extended hours and weekends to meet critical deadlines, as needed
- To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here
- Develop/support automated block and full chip level advanced timing/noise signoff flows (with advanced and parametric on chip variation, and voltage drop aware STA)
- Define block and full chip timing signoff criterion, methodology, constraints, modes and scenarios and close timing at multi-corner and multi-mode environments
- Develop/support signoff STA timing/power optimization engineering change order flows and integrate them into physical design flow
- Work with systems and architecture, SOC integration, verification, DFT, mixed signal, IP owners, synthesis, and place/route teams to address the design challenges in the context of timing sign-off
- Generate block timing begets, clock and I/O context files
- Debug and drive fixing of constraint correlation issues between top and block level
- Develop clock network simulation and jitter analysis methodologies
- Drive custom IP integration, custom timing check flow enablement and closure until tapeout
- Guide full chip team to plan and build reference/special clock trees for minimal jitter and insertion delay
- Develop and run block/full chip level noise analysis flows and drive the noise/signal integrity closure with block and full chip engineers
- Work with voltage drop, architecture, package teams to understand voltage drops, guard banding requirements, voltage and library selection for signoff STA and noise analysis
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