Senior Staff / Principal SoC Floorplan Lead
No salary listed
Expert
Bachelor's, Master's, PhD
Bengaluru, Karnataka, India
In Person
Hardware EngineeringSilicon & ASIC Design
About the job
Requirements
- At least 12 years of hands-on experience in physical design SoC floorplanning, preferably in the data center domain, including at least 3 years as a lead or primary owner of SoC-level floorplanning.
- A proven track record of taping out large, complex chips for data center, networking, or artificial intelligence and machine learning applications.
- Deep understanding of how Register-Transfer Level structures and architectural decisions affect physical design power, performance, and area.
- Extensive experience with bump planning, flip-chip package requirements, and die-to-package co-optimization.
- Strong knowledge of analog/mixed-signal intellectual property integration, shielding, and custom routing constraints.
- Expertise with industry-standard physical design tools, specifically Cadence Innovus.
- A Bachelor of Science, Master of Science, or Doctor of Philosophy in Electrical Engineering, Computer Engineering, or a related field.
Responsibilities
- Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale artificial intelligence and data center chips on advanced process nodes such as 5 nanometers and 3 nanometers or below.
- Partner with architecture and Register-Transfer Level teams to provide early physical feasibility feedback, drive block partitioning and shape optimization, and plan data flow to optimize power, performance, and area.
- Lead bump planning and input/output ring definition, and work with packaging teams on flip-chip and advanced packaging constraints to optimize signal escape and power delivery.
- Manage placement and custom routing strategies for critical analog/mixed-signal intellectual property, high-speed SerDes, including PCIe and Ethernet, memory interfaces, phase-locked loops, and sensitive clock distributions.
- Design and analyze the top-level power delivery network, ensuring robust power delivery for high-current artificial intelligence workloads while minimizing IR drop.
- Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion.
- Build and maintain scalable floorplanning workflows and scripts using Tool Command Language and Python.
Desired Qualifications
- Experience with multi-die or chiplet integration, including 2.5D packaging, 3D packaging, interposers, or Universal Chiplet Interconnect Express.
- Strong scripting and automation skills using Tool Command Language, Python, Perl, and Makefile.
- Knowledge of advanced clocking architectures, including H-trees and meshes, for highly synchronous artificial intelligence fabrics.
About the company
EnCharge AI develops hardware and software for artificial intelligence computation, ranging from edge devices to cloud servers. The company utilizes analog in-memory computing through chiplets, ASICs, and PCIe cards to process AI tasks directly within memory, which reduces the power and space required for complex calculations. Unlike competitors using traditional digital methods, EnCharge AI offers significantly lower CO2 emissions and a lower total cost of ownership by integrating its specialized technology into the existing semiconductor supply chain. The company's goal is to democratize advanced AI by making it economically viable and sustainable for businesses to solve large-scale human challenges.
Company Size
51-200
Company Stage
Series B
Total Funding
$162.9M
Headquarters
Santa Clara, California
Founded
2022
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Simplify's Take
What believers are saying
- EN100 launched May 29, 2025 for laptops, workstations, and edge devices.
- Fast Company recognized EnCharge in 2026 World Changing Ideas, boosting brand visibility.
- Samsung Ventures, Foxconn-linked HH-CTBC, RTX Ventures, and Princeton expand distribution and partnerships.
What critics are saying
- EN100 lacks independent benchmark validation against Nvidia and AMD as of launch.
- Round 1 early access is full, but commercial scale still depends on OEM adoption.
- Analog compute commercialization has execution risk; one silicon bug can delay 2025 revenue.
What makes EnCharge AI unique
- EN100 uses analog in-memory computing for 200+ TOPS at 8.25W.
- Tiger Global led EnCharge's $100M Series B on February 13, 2025.
- DARPA's OPTIMA grant with Princeton validates EnCharge's technical credibility and defense relevance.
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Benefits
- Health Insurance
- 401(k) Retirement Plan
- Remote Work Options