Responsibilities

• Architecture of Tenstorrent’s IP blocks including aggressive optimization for performance, power, and area
• Implementation of Tenstorrent IP RTL logic in Verilog
• Contribution to verification of Tenstorrent’s IP and SOC logic
• Performance and power verification and validation of Tenstorrent’s IP and SOC

Experience & Qualifications

• Versatility, independent thinking, and general ability to get things done!
• 15+ years of experience working on high performance IP and ASIC designs
• Bachelor/Masters/PhD in Electrical/Computer Engineering/Engineering Science
• Expert knowledge of Hardware Description Languages (Verilog/VHDL)
• Comfortable with C++
• Deep and broad understanding of processor/computer architecture
• Knowledge and understanding of the full ASIC design flow
• Experience with any of high frequency logic design, scalar and vector processor architecture, GPU architecture and programming models, digital signal processing hardware, SoC architecture, memory subsystem architecture, real time hardware/firmware systems or deep learning is very beneficial