Full-Time

Senior ASIC/VLSI Synthesis and Design Engineer

Confirmed live in the last 24 hours

Celestial AI

Celestial AI

51-200 employees

Silicon photonics for high-performance computing

AI & Machine Learning
Hardware

Compensation Overview

$175,000 - $195,000Annually

Senior

Irvine, CA, USA

Required Skills
Verilog
Python
Perl
Requirements
  • Bachelor's/Master's degree in Electrical/Electronic Engineering or Computer Science
  • At least 10 years of experience in ASIC/VLSI design, with a focus on synthesis, design, and DFT
  • Strong understanding of digital design principles, and experience with RTL coding in Verilog/SystemVerilog
  • In-depth knowledge of synthesis methodologies and tools from leading EDA vendors (Genus, Tempus, DC, PrimeTime, etc)
  • Experience with writing design constraints for synthesis, timing closure, gate level simulation, and pipelining at different levels for performance optimization and timing closure
  • Experience with DFT flows, including scan insertion and ATPG
  • Familiarity with physical design and backend flow
  • Experience with power analysis and optimization flows such as power gating, clock gating, voltage scaling, and dynamic voltage frequency scaling
  • Experience with memory BIST and repair, and post-silicon validation
  • Experience with deep technology nodes and very large designs
  • Experience with scripting languages such as Perl, Python, or Tcl
  • Excellent problem-solving skills and ability to work independently and in a team environment
  • Strong communication and interpersonal skills, with the ability to interact effectively with cross-functional teams
  • Proven track record of delivering successful designs on time and meeting performance, power, and area goals
Responsibilities
  • Develop and implement high-performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools
  • Work closely with design teams to understand the requirements and constraints of the design, and provide feedback on design feasibility, timing, and power
  • Write and implement block level and top level constraints for synthesis, perform timing closure, and gate level simulation
  • Develop and implement synthesis flows and methodologies, and drive improvements in the design process
  • Debug and resolve design issues related to synthesis, timing, power, and area
  • Design and support DFT flows, including scan insertion and ATPG
  • Optimize designs for power, performance, and area, and meet design goals within the given schedule. Implement memory BIST and repair, and support post-silicon validation
  • Implement pipelining at different levels for performance optimization and timing closure
  • Perform power analysis and optimize designs for low power

Celestial AI has developed the Photonic Fabric™ technology platform, utilizing silicon photonics for data movement within and between chips, enabling high-performance computing solutions with differentiated single node performance and efficient scalability for multi-node and multi-model applications. The platform leverages integrated silicon photonics for data movement, providing significant performance gains for machine learning and high-performance computing applications, with a projected addressable market exceeding $70 billion in 2025.

Company Stage

Series C

Total Funding

$337.9M

Headquarters

Santa Clara, California

Founded

2020

Growth & Insights
Headcount

6 month growth

20%

1 year growth

32%

2 year growth

190%