Core Regression Debug Lead Engineer

Updated on 5/24/2023

Locations

Austin, TX, USA

Experience Level

Entry

Junior

Mid

Senior

Expert

Desired Skills

C/C++/C#

Perl

Python

Verilog

VHDL

Requirements

BS/MS/PhD in EE/ECE/CE/CS with at least 10 years of experience
Strong background and experience with high performance OOO CPU microarchitecture
Experience and understanding of one or more ISAs - x86, ARM or RISCV
Significant experience debugging RTL and DV in a simulation environment, proficient at waveform and log file based debug
Experienced with assembly, C/C++ and UVM based stimulus generation targeting both ISA and microarchitectural scenarios
Familiar with simulation, formal and emulation environments
Hands-on with scripting (Python, PERL)
Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities

Functional verification with emphasis on core level regression debug and triage for simulation and emulation regressions
Hands-on debug for core level failures. Propose and implement stimulus enhancements and debug capability improvements for core, cluster and chip level testbench environments
Primary owner for driving bug hunting using all available stimulus generators. Analysis of bugs found and proposing not only stimulus but also configuration and coverage changes
Drive core level regression environment enhancements to improve the overall productivity for the team
Develop detailed core level verification plans by understanding both ISA and microarchitectural specifications for the design
Support design deployment across simulation and emulation platforms
Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
Work with design, test and post silicon validation teams to ensure high quality delivery of the entire CPU core / cluster

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Lead CPU verification engineer driving core level regression debug, triage and responsible for the functional sign-off for the core.

Responsibilities

Functional verification with emphasis on core level regression debug and triage for simulation and emulation regressions
Hands-on debug for core level failures. Propose and implement stimulus enhancements and debug capability improvements for core, cluster and chip level testbench environments
Primary owner for driving bug hunting using all available stimulus generators. Analysis of bugs found and proposing not only stimulus but also configuration and coverage changes
Drive core level regression environment enhancements to improve the overall productivity for the team
Develop detailed core level verification plans by understanding both ISA and microarchitectural specifications for the design
Support design deployment across simulation and emulation platforms
Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
Work with design, test and post silicon validation teams to ensure high quality delivery of the entire CPU core / cluster

Experience & Qualifications

BS/MS/PhD in EE/ECE/CE/CS with at least 10 years of experience
Strong background and experience with high performance OOO CPU microarchitecture
Experience and understanding of one or more ISAs - x86, ARM or RISCV
Significant experience debugging RTL and DV in a simulation environment, proficient at waveform and log file based debug
Experienced with assembly, C/C++ and UVM based stimulus generation targeting both ISA and microarchitectural scenarios
Familiar with simulation, formal and emulation environments
Hands-on with scripting (Python, PERL)
Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
Strong problem solving and debug skills across various levels of design hierarchies

Multiple geographies: Austin, Santa Clara, Bangalore

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

51-200 employees

Website

Computer processor architecture manufacturer

Company Overview

Tenstorrent is on a mission to address the rapidly growing compute demands for software 2.0. The company designs processors that are optimized for neural network inference, training and can also execute other types of parallel computation.

Company Core Values

Collaboration
Curiosity
Commitment to solving hard problems