Full-Time
Senior RTL Design Engineer
CPU
SiFive
501-1,000 employees
Designs and sells RISC-V semiconductor cores
No salary listed
Cambridge, UK
In Person
On-site in Cambridge, United Kingdom. Must have right to work in the United Kingdom.
Bachelor's, Master's
 Hardware Engineering (1) |
|---|
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- BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
- 3+ years of design experience.
- Academic or professional experience with CPU RTL design.
- Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
- Strong software engineering skills/background, including: Object-oriented, aspect-oriented, and particularly functional programming; Templated metaprogramming, in any language; Compiler infrastructures, particularly for domain-specific languages; Data modeling, particularly intermediate representations for optimizing or transforming compiler passes; Test-driven development, particularly ability to write adaptive unit tests.
- Attention to detail and a focus on high-quality design.
- Ability to work well with others and share the belief that engineering is teamwork
- Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
- Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
- Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
- Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
- Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
- Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
- Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.
- Knowledge of RISC-V architecture.
- Expertise in CPU processor designs in one or more of the following areas is a plus: instruction fetch; instruction decode; register renaming and instruction scheduling; vector units; load-store unit.
- Knowledge of verification principles, testbenches, UVM, and coverage.
- Experience with Git/Github, Jira, Confluence.
SiFive designs and sells RISC-V based processors and related semiconductor IP. Its cores and system-on-chip designs use the open RISC-V instruction set, allowing customers to integrate high-performance, energy-efficient computing into autos, data centers, wearables, and other devices. By leveraging an open standard, SiFive offers flexible, scalable, and cost-effective solutions that can pack more compute density into smaller chips with lower power use. The company aims to grow the RISC-V ecosystem and help customers tackle data-intensive workloads across industries with practical, deployable hardware.
Company Size
501-1,000
Company Stage
Series G
Total Funding
$772.5M
Headquarters
San Mateo, California
Founded
2015
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Simplify's Take
What believers are saying
- April 9, 2026 raised $400 million at $3.65 billion from Nvidia, Atreides, Apollo.
- May 12, 2026 P570 Gen 3 targets edge AI, consumer IoT, and commercial IoT.
- HighTec’s May 7, 2026 safety-toolchain partnership expands automotive and industrial adoption.
What critics are saying
- SiFive still sells blueprints, not chips; customers can internalize IP and bypass it.
- Arm’s March 2026 chip push targets SiFive’s customers in data-center CPUs.
- A failed IPO after April 9, 2026 funding leaves SiFive dependent on dilutive private capital.
What makes SiFive unique
- SiFive owns pure-play RISC-V IP, unlike Arm’s licensing model and chip sales.
- May 12, 2026 P570 Gen 3 adds RVA23, vector, and security features.
- SiFive’s April 9, 2026 NVLink Fusion ties RISC-V CPUs to Nvidia GPUs.
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Benefits
Health Insurance
401(k) Retirement Plan
Paid Vacation
Company Equity
Growth & Insights and Company News
6 month growth
↓ -1%1 year growth
↓ -1%2 year growth
↑ 0%SiFive has launched the Performance P570 Gen 3, a high-performance RISC-V processor core targeting edge AI, consumer and commercial IoT applications. The chip delivers 13% better performance on traditional CPU workloads with 13% lower power consumption compared to the P550 Gen 1, whilst AI workloads see up to 21 times improvement. The P570 Gen 3 features a 3-wide, 13-stage out-of-order superscalar pipeline and an upgraded 128-bit vector engine. It fully supports the RVA23 profile, backed by Google, Red Hat and Canonical, ensuring compatibility with mainstream operating systems including Android and Linux. The processor is available today and scales up to 16 cores. SiFive also updated the P550 Gen 3 for customers requiring smaller area budgets without vector capabilities.
SiFive sets new bar for high-performance RISC-V with third-generation performance P550 and P570 IP. * Business Wire * May 12, 2026 * 0 SANTA CLARA, Calif.-(BUSINESS WIRE)-May 12, 2026- SiFive, Inc., the gold standard for RISC-V computing, today announced the launch of the SiFive Performance(TM) P570 Gen 3, the most powerful and efficient out-of-order processor core in its class. Purpose-built for demanding edge AI, high-end consumer, and commercial IoT applications, the P570 Gen 3 delivers a large leap in performance compared to the popular P550 Gen 1, and also provides the most modern RVA23 ISA profile support. This versatile IP can be used as the control processor in embedded IoT devices, running a full networking stack, or can be used as the main applications processor in consumer devices, running rich OSs, such as Android or enterprise-grade Linux. The high-performance vector unit supports running AI models and inference on edge devices. "The P570 Gen 3 is built to meet the demands for today's most demanding consumer and commercial applications," said Krste Asanovic, SiFive co-Founder and Chief Architect. "With world-class RVA23 capabilities, the new P570 IP will meet next-generation customer requirements for high performance with leading area and power efficiency. This enables tremendous new possibilities coupled with the capability to work most of the major operating systems." Industry-Leading Performance and Efficiency The P570 Gen 3 introduces significant architectural improvements, featuring a 3-wide, 13-stage fully out-of-order superscalar execution pipeline and an upgraded vector engine. * Traditional CPU workloads: 7- 13% performance improvement on SpecInt 2006-2017 combined with a 13% reduction in dynamic power vs. P550 Gen 1 * Modern AI CPU workloads: The 128-bit VLEN vector pipeline delivers a 2X increase in Geekbench and up to 21X more performance in specific AI-relevant workloads vs. Gen 1, and up to 4.5X vs. Gen 2, utilizing specialized dot-product instructions to accelerate convolution and matrix-multiply operations. More Than Just the Core SiFive also provides a complete solution around the P570 core including system IP, such as the RISC-V standard-compliant advanced interrupt architecture (AIA), WorldGuard to support trusted execution environments on secure SoCs, and a second-generation RISC-V standard-compliant IOMMU. P570 Gen 3 is also scalable up to 16 cores in a compute subsystem. A New Baseline for RISC-V Standardization The P570 Gen 3 is fully compliant with the RVA23 profile (backed by major ecosystem players, including Google, Red Hat, and Canonical), providing software developers with a stable, consistent set of instructions and ensuring the P570 is ready for mainstream application development. As well as supporting all the RVA23 mandatory requirements, including the Hypervisor (H) and Vector (V) extensions, the P570 includes optional extensions for enhanced security and management, and support for FP16 and BF16 to accelerate modern AI workloads. The additional security features include secure branch prediction and RISC-V standard Vector Crypto (both NIST and SM) and Enhanced Protected Memory (smepmp) extensions. The P570 is available today and we are working with customers in several market segments. The P570 is ideal for use cases requiring high-performance and power efficiency in a small area budget. For customers with very strict area constraints who don't require vectors, the updated P550 Gen 3 provides a highly efficient RVB23-compatible core. Download the product brief Here Partner Support: "Canonical has led in making RISC-V a first-class citizen, and the launch of the SiFive Performance(TM) P570 Gen 3 is a pivotal moment for the ecosystem," said Cindy Goldberg, VP Cloud and Silicon Partnerships at Canonical. "By aligning with the RVA23 profile, the P570 leverages the standardized foundation provided by Ubuntu 26.04 LTS, ensuring that P570 adopters have access to enterprise-grade long-term support, security and stability." Imagination Technologies "A GPU is a must-have for any consumer and embedded SoC looking to deliver great visual experiences," said Markus Mosen, CEO at Imagination Technologies. "Our long-standing collaboration with SiFive means that P570 Gen 3 customers can rely on proven RISC-V CPU and GPU combinations that integrate seamlessly and shorten time to market." Lauterbach "Lauterbach was an early supporter of RISC-V and continues to actively contribute to its standardization through RISC-V International, with a long track record of supporting processors from SiFive," said Rolf Kühnis, Strategic Technical Alliance Manager, Lauterbach. "Leveraging the same debug interface as the earlier generations of Performance processors provides a seamless path for existing users to adopt the new P570 Gen 3 IP, while offering a low-risk migration path to RISC-V for new customers." "Red Hat and SiFive share a mutual commitment to enabling the developer community. This latest milestone further underscores how SiFive continues to drive innovation in the RISC-V ecosystem. Their dedication to the RVA23 profile, showcased in the new P570 Gen 3, provides a stable, consistent foundation that is essential for accelerating mainstream application development and the future adoption of RISC-V." - Ronald Pacheco, Senior Director of Red Hat Enterprise Linux Product & Ecosystem Strategy, Red Hat "RISCstar is actively collaborating with SiFive and the RISC-V Software Ecosystem (RISE) to upstream a full-featured implementation of OP-TEE for RISC-V," said Joe Bates, CEO of RISCstar. "We're proud of our work with SiFive building an optimized TEE for the P570 Gen 3 that supports secure, scalable deployments across embedded, digital consumer, and industrial Linux use cases and markets." SiFive Corporate Communications:[email protected] KEYWORD: CALIFORNIA UNITED STATES NORTH AMERICA INDUSTRY KEYWORD: SOFTWARE HARDWARE ELECTRONIC DESIGN AUTOMATION ARTIFICIAL INTELLIGENCE TECHNOLOGY IOT (INTERNET OF THINGS) SEMICONDUCTOR SECURITY PUB: 05/12/2026 09:00 AM/DISC: 05/12/2026 09:04 AM 00:00/00:57
HighTec EDV-Systeme and SiFive: Together strengthening the RISC-V Ecosystem for Safe and Secure Automotive and Industrial Applications. Saarbruecken, Germany, May 7, 2026 - HighTec EDV-Systeme, a leading provider of automotive compiler solutions, is collaborating with SiFive, a leading supplier of high-performance RISC-V processor IP, to accelerate safety-ready RISC-V software development for automotive and industrial systems. The partnership brings together HighTec's safety-qualified LLVM-based toolchains for Rust and C/C++, and SiFive's safety-focused RISC-V IP. This joint offering enables software developers to adopt RISC-V more efficiently through an integrated approach to safety, security, performance, and scalable software development. Reduce integration effort The shift towards software-defined architectures in automotive and industrial systems is fueling demand for open and flexible platforms with strong safety features. RISC-V's open instruction set architecture (ISA) enables innovation and customization, while supporting the highest safety, security, and performance requirements. The combination of HighTec's qualified toolchains with SiFive's safety-focused RISC-V IP enables software developers to simplify their integration and shorten time to production for their safety-relevant RISC-V designs. High performance meets safety The HighTec Rust and C/C++ toolchain is qualified according to the highest functional safety standard ISO 26262 up to ASIL D and the cybersecurity standard ISO 21434, enabling the rapid generation of high-performance code for safety-critical automotive and industrial applications. Built on advanced LLVM technology, the toolchain supports SiFive's advanced RISC-V IP and tuned performance enhancements, enabling hybrid development that combines legacy C/C++ code with modern Rust. HighTec's comprehensive Qualification Kit helps to accelerate and simplify tool qualification, supporting safety and security certification activities. SiFive's automotive-focused RISC-V processor IP delivers scalable performance with built-in support for functional safety and security requirements. Designed for safety-critical automotive and industrial applications, these cores enable efficient system integration while supporting long product lifecycles and certification needs. "The RISC-V ecosystem continues to grow rapidly, and we are pleased to have the support of HighTec's open-source-based compiler technology for our RISC-V cores", said John Ronco, SVP of Product, SiFive. "Together, through close collaboration we enable developers to optimize performance while addressing functional safety requirements and significantly reducing time to production." "HighTec is highly committed to open standards such as RISC-V and open-source technologies like LLVM as we see them as key drivers for safe and secure innovations in modern embedded systems", said Mario Cupelli, CTO of HighTec EDV-Systeme GmbH. "With our safety- and security-qualified toolchains and strong technology partners like SiFive, we bring these technologies into safety-critical automotive and industrial applications, enabling scalable software platforms and accelerating adoption of RISC-V across the ecosystem." About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of computing by bringing the power and flexibility of RISC-V to the world. SiFive's market-leading IP provides the blueprint for high-performance, customizable, and energy-efficient processor cores across the entire computing spectrum, from the intelligent edge to the most advanced AI data centers. For more information, visit www.sifive.com About HighTec EDV-Systeme GmbH HighTec EDV-Systeme GmbH, Saarbruecken/Germany, is the world's leading commercial provider of compiler solutions built on cutting edge open-source technologies. For over three decades, HighTec has been pioneering the transformation of open-source software into automotive- and industrial grade solutions. The company offers ISO 26262 ASIL D certified tools for embedded software development, the PXROS-HR real-time operating system, and a comprehensive suite of design-in services. HighTec's ASIL D qualified Rust and C/C++ compilers for leading multicore microcontrollers in the automotive and industrial sectors, including Arm(R), TriCore(TM)/AURIX(TM)/TRAVEO(TM), Renesas RH850, RISC-V, Power Architecture (PowerPC), and Embedded AI accelerators, are continuously adapted and optimized for new architectures through close cooperation with silicon partners. In addition to the multi-architecture compiler, HighTec offers PXROS-HR, a safety-certified multicore RTOS for applications with safety and multicore requirements. PXROS-HR guarantees robustness, safety, high performance, and data security in real-time environments. PXROS-HR is certified according to ISO 26262 ASIL D / IEC 61508 SIL 3 and is complemented for ASIL D development by a Tool Qualification Kit as a basis for the certification of customer applications. Complementing this portfolio, HighTec offers development, training and consulting services. Founded in 1982, HighTec is a privately held company and operates offices in Germany (headquarters), Hungary, China, and the United States, providing global reach combined with strong local engineering support. Please connect with HighTec EDV-Systeme GmbH on LinkedIn.
Nvidia backs SiFive at $3.65B: RISC-V enters data center battle. 5 hours ago 0 On April 9, 2026, SiFive raised $400 million in a Series G funding round at a $3.65 billion valuation, with Nvidia joining as a new strategic investor. Led by Atreides Management and backed by Apollo Global Management, Point72 Turion, and T. Rowe Price, this oversubscribed round marks SiFive's final private raise before an anticipated IPO. The significance isn't just the money - it's Nvidia's strategic bet that RISC-V, the open-source CPU architecture, is ready for AI data centers. RISC-V CPUs can now plug into Nvidia's GPU infrastructure through NVLink Fusion, and Nvidia is porting CUDA to the RISC-V RVA23 profile. This puts RISC-V on equal footing with x86 and ARM in AI workloads. For developers, that's the headline: the open-source instruction set architecture just became a viable alternative to Intel, AMD, and ARM in the one market that matters most - AI infrastructure. Why Nvidia is betting on RISC-V. Nvidia doesn't make CPUs, but it needs a healthy CPU ecosystem to sell GPUs. X86 is controlled by Intel and AMD (competitors), and ARM's licensing model creates friction. RISC-V offers Nvidia a neutral, open partner with no vendor lock-in. The numbers back Nvidia's bet. RISC-V hit 25% global market share in 2026, up from 2.5% in 2021. Meta acquired Rivos, Qualcomm bought Ventana Micro for $2.4 billion, and Google is porting its software stack to RISC-V. This is strategic infrastructure planning by hyperscalers breaking the x86/ARM duopoly. In January 2026, SiFive integrated Nvidia's NVLink Fusion, enabling coherent connectivity between RISC-V CPUs and Nvidia GPUs. Combined with Nvidia's CUDA port to RISC-V, the last technical barrier to enterprise adoption is gone. System builders can now choose x86, ARM, or RISC-V CPUs for Nvidia's AI infrastructure - and RISC-V is the only option with zero licensing fees. Open source hardware's Linux moment. RISC-V's trajectory mirrors Linux disrupting proprietary Unix: no licensing fees, no vendor lock-in, freedom to customize. Companies building AI data centers can add domain-specific instructions for AI workloads without waiting for Intel, AMD, or ARM's roadmap. The technical advantages matter. RISC-V's modular design reduces power consumption - critical for massive AI clusters. SiFive's data center CPUs target 200W TDP versus 250W for comparable x86 chips. For hyperscalers spending billions on power infrastructure, that efficiency gap compounds. Real-world adoption is accelerating. Meta, Qualcomm, and Google are deploying RISC-V internally, and the automotive industry standardized on RISC-V through the Quintauris joint venture (Bosch, BMW, Infineon, NXP, Qualcomm) in early 2026. Industry analysts predict RISC-V-native data centers will emerge by 2027. IPO plans signal ecosystem maturity. CEO Patrick Little confirmed to Reuters that the April 2026 Series G is SiFive's final private round before an IPO, though no exchange or timeline has been announced. At $3.65 billion, SiFive is the most valuable pure-play RISC-V company. SiFive reported record growth in 2025, with over 500 semiconductor designs and 10+ billion RISC-V cores shipped, targeting a $100+ billion addressable market in data center CPUs. An IPO validates the entire RISC-V ecosystem. Public markets don't bet on science projects - if SiFive goes public, it proves open-source CPU architectures can compete with Intel, AMD, and ARM in data centers. What developers should watch. RISC-V isn't vaporware. The toolchain is ready: GCC and LLVM have full support, major operating systems run on RISC-V, and Nvidia's CUDA port means GPU-accelerated workloads will work. Developers should add RISC-V targets to CI/CD pipelines for future-proofing, watch for RISC-V instance offerings from AWS, Google Cloud, and Azure by 2028-2029, and monitor AI framework support as TensorFlow and PyTorch add RISC-V optimizations. The performance trade-off is real. Early RISC-V chips lag x86 and ARM in single-threaded workloads but excel in power efficiency and massively parallel AI tasks. The sweet spot is AI inference and training, not general-purpose computing - yet. ARM isn't sitting still. Industry projections suggest ARM will power 90% of AI servers using custom processors by 2029, leaving 10% for x86 and RISC-V combined. RISC-V is credible, not dominant. The takeaway. Nvidia's $400 million bet isn't about RISC-V replacing x86 or ARM tomorrow - it's about breaking the duopoly and ensuring Nvidia has a neutral, open CPU partner. RISC-V hit 25% market share, secured a $3.65 billion valuation, and cleared the IPO bar. For developers, RISC-V support is coming to your tools, frameworks, and cloud providers. Whether it becomes dominant or a strong third pillar alongside x86 and ARM, ignoring RISC-V in 2026 means ignoring where AI infrastructure is headed. Open-source hardware is following the same trajectory as open-source software - slow adoption, then sudden ubiquity. I am a playful and cute mascot inspired by computer programming. I have a rectangular body with a smiling face and buttons for eyes. My mission is to cover latest tech news, controversies, and summarizing them into byte-sized and easily digestible information.
The deal is interesting for a number of reasons, including that SiFive's chip designs are based on RISC-V, not x86 or ARM.