Senior FPGA Engineer

Job Description

Reporting to the Manager of FPGA – Imaging, this Engineer will play a role in delivering best-in-class image/video processing solutions for our da Vinci systems (and other robotic platforms), as part of an excellent cross-functional team. The engineer in this position will work with the broader Vision and EE teams to architect, implement and verify image sensor interfaces and image processing algorithms on FPGAs / FPGA SoCs deployed on the platform. This includes components in the entire processing chain, photon-to-photon: from image sensor data acquisition to stereo (and mono) displays.

The ideal candidate will possess a proven background in FPGA-based video/image processing with exposure to typical image processing algorithms and image sensor interfaces – implementation and evaluation with the trade-offs between visual quality, performance, and FPGA resource utilization in mind.

Responsibilities

• Define and implement high-performance image/video processing pipelines in FPGAs
• Collaborate with other experts in imaging to craft the best trade-offs in resources, cost, performance, and practicality to create optimal video processing architectures
• Work with other contributors in the FPGA space to harmonize the video processing implementation with established best practices
• Implement designs using (System)Verilog and C/C++ (High Level Synthesis)
• Verify implemented designs in simulation and on hardware
• Collaborate on improvements to FPGA design and verification methodology; investigate new technologies that would reduce development / verification time
• Explore and evaluate new FPGA / FPGA-SoC platforms for low-latency video processing

Qualifications

Required Education, Skills and Experience

• 8 years of related experience and a Bachelor's degree; or 6 years experience and a Master's degree; or a PhD with 3 years experience; or equivalent experience
• Experience with SystemVerilog, C (or C++) and a scripting language such as Python or TcL
• Experience with Vitis HLS or other high-level synthesis tools
• Understanding of and experience with high-speed digital design and associated challenges
• Foundation in using FPGA build tools such as: AMD/Xilinx, Intel and/or Lattice
• Foundation in using FPGA simulation tools, environments and in test bench development
• Understanding of static timing analysis / timing constraints
• Experience with FPGA part and pin selection process
• Familiar with common image processing techniques
• Experience with revision control software e.g. Git
• Willingness to learn new skills and embrace emerging technologies

Desired Skills and Experience

• Experience with Versal Prime / Premium / Edge Series
• Exposure to, or experience with AIE-ML tiles on Versal Edge devices