Full-Time

Principal Signal Power Integrity Engineer

Texas Institute for Electronics

University of Texas at Austin

University of Texas at Austin

No salary listed

Company Does Not Provide H1B Sponsorship

Austin, TX, USA

Hybrid

Hybrid work possible; travel up to 30–50%. Working outside Texas requires university review.

Category
Electrical Engineering (2)
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Requirements
  • BS in Electrical Engineering, Computer Engineering, Applied Physics, or related discipline.
  • 12+ years of direct, hands-on experience in signal integrity and/or power integrity engineering for advanced packaging, 2.5D/3DIC, or heterogeneous integration platforms.
  • Deep expertise with SI/PI and EM extraction tools: Ansys HFSS/SIwave, Cadence Sigrity/Clarity 3D, Synopsys RaptorX, Keysight ADS/PathWave, Siemens HyperLynx, or equivalent.
  • Proven ability to build and deliver package-level electrical models (S-parameters, broadband RLCK, dielectric characterization) and integrate them into design enablement and signoff flows.
  • Strong understanding of high-speed signaling fundamentals: transmission-line theory, impedance matching, return-path management, crosstalk mechanisms, ISI/jitter decomposition, and equalization techniques.
  • Experience with PDN design methodology: target impedance, decap optimization, plane resonance, IR-drop analysis, and SSN/SSO mitigation in multi-die environments.
  • Hands-on scripting and automation skills (Python, Tcl, SKILL, etc.) to streamline simulation and extraction flows.
  • You’re able to work with ambiguity, act with urgency, and take personal ownership for outcomes. Ability to make things happen.
  • Execution mindset. You have demonstrated experience working in a hands-on role driving progress across multiple initiatives without layers of management.
  • Location. Austin, Texas is preferred for close collaboration with our engineering teams and partners. Hybrid work arrangements may be possible, with travel up to 30–50% as needed. (Any flexible arrangement would be subject to university policies and approvals. Working outside of the state of Texas is subject to University review and approval in relation to jurisdictional employment and tax related laws, rules, and regulations.
Responsibilities
  • Own and drive signal integrity and power integrity (SI/PI) analysis end-to-end for advanced 2.5D/3.0D heterogeneous integration packages—from initial interconnect architecture through silicon-package co-design to final signoff.
  • Perform high-speed interconnect modeling and extraction (S-parameters, RLCK, transmission-line models) across TSVs, micro-bumps, hybrid bonds, RDL, and advanced substrates (silicon, glass, organic).
  • Architect and optimize power delivery networks (PDN) for multi-chiplet 3D stacks—including target impedance analysis, decoupling strategy, IR-drop simulation, and PDN resonance identification from die through package to board.
  • Execute full SI simulation workflows: EM extraction, crosstalk analysis, eye diagram/BER prediction, channel compliance simulation, and jitter budgeting for high-speed interfaces (PCIe Gen6/7, CXL, UCIe, SerDes, HBM).
  • Build and validate SI/PI models for the 3D Assembly Design Kit (ADK)—creating accurate, reusable electrical models that enable chiplet designers to perform system-level co-design against TIE’s integration platform.
  • Develop reference flows, scripts, and automation that make SI/PI enablement repeatable and accessible to internal design teams and external customers.
  • Collaborate directly with EDA vendors (Cadence, Ansys, Synopsys, Siemens, Keysight), OSATs, and foundries to develop, benchmark, and refine package-level SI/PI simulation flows and tool interoperability.
  • Track and incorporate requirements from next-gen interface standards (UCIe, PCIe, CXL, UALink, OIF-CEI, HBM) into package design rules and SI/PI methodology.
  • Guide technical strategy for SI/PI at TIE, mentor engineers, and represent TIE in industry standards bodies, customer design reviews, and technical forums.
Desired Qualifications
  • MS or PhD in Electrical Engineering, Applied Physics, or related discipline.
  • Deep experience with multi-material package SI/PI challenges (Si interposers, glass substrates, organic build-up, Cu pillar/hybrid bond transitions) and their impact on signal loss, impedance control, and PDN performance.
  • Demonstrated expertise in channel compliance and link-budget analysis for PCIe, CXL, UCIe, SerDes, or HBM, including silicon–package–board co-simulation.
  • Familiarity with industry standards and working groups (IEEE, JEDEC, OIF, UCIe Consortium, 3Dblox, JEP30).
  • Working knowledge of thermal and mechanical co-simulation and how thermo-mechanical effects (warpage, stress, CTE mismatch) influence SI/PI performance in 3D stacks.
  • Experience creating or contributing to PDK/ADK simulation collateral for SI/PI design enablement.
  • Track record of technical publications, patents, or open-source contributions in signal integrity, power integrity, or high-speed package design.
University of Texas at Austin

University of Texas at Austin

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