DFT manager
Posted on 3/22/2024
Rivos

201-500 employees

High performance CPUs & RISC-V
Company Overview
Rivos is a startup in stealth-mode.
Hardware

Company Stage

Series A

Total Funding

$120M

Founded

2021

Headquarters

Mountain View, California

Growth & Insights
Headcount

6 month growth

1%

1 year growth

9%

2 year growth

41%
Locations
Austin, TX, USA • Santa Clara, CA, USA • Fort Collins, CO, USA • Portland...
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
Python
Perl
Data Analysis
CategoriesNew
Hardware Engineering
Electronic Hardware Engineering
Hardware Validation & Testing
Requirements
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Minimum of 15+ years of experience in DFT, with focus on digital and mixed signal designs in the semiconductor industry.
  • Strong proficiency in DFT tools
  • Experience with ATPG, scan insertion, and test pattern generation for high-complexity designs.
  • Hands-on experience with DFT-related EDA tools and methodologies, including scan compression, boundary scan, memory BIST, and JTAG.
  • Familiarity with silicon bring-up and post-silicon debug.
  • Strong knowledge of DFT techniques, methodologies, and industry standards, such as IEEE 1149.1.
  • Experience in scripting languages, such as Perl or Python, for automation and data analysis is desirable.
  • Strong analytical and problem-solving skills, with the ability to identify and address DFT-related issues and challenges.
  • Excellent communication and leadership abilities, with a track record of successfully leading teams and collaborating with cross-functional stakeholders.
  • Self-motivated and detail-oriented, with a commitment to delivering high-quality results within established timelines.
Responsibilities
  • Develop and execute DFT methodologies, strategies, and guidelines to maximize test coverage, reduce test cost, and optimize production yield.
  • Define and review DFT specifications, including scan, test compression, boundary scan, memory BIST, and ATPG patterns, ensuring compliance with industry standards.
  • Evaluate and select appropriate DFT methodologies, considering design complexity, test coverage requirements, and time-to-market constraints.
  • Work closely with the design team to influence design decisions and ensure DFT requirements are met without compromising performance, power, or area.
  • Lead and manage the DFT team, providing technical guidance and mentorship to engineers, ensuring their professional growth and development.
  • Collaborate with cross-functional teams, including design, verification, and manufacturing, to define DFT requirements and drive DFT implementation throughout the product lifecycle.
  • Drive continuous improvement initiatives to enhance DFT methodologies, tools, and processes, aiming for increased efficiency, quality, and reliability of DFT implementation.
  • Perform DFT sign-off activities, including DFT coverage analysis, ATPG fault coverage analysis, DFT-related timing analysis, first-pass silicon bring-up and post-silicon debug.
  • Stay abreast of industry trends, emerging DFT techniques, and advancements in semiconductor testing, and apply relevant knowledge to improve DFT practices within the organization.