Full-Time
Distinguished Product Quality Engineer
Posted on 8/27/2025
Astera Labs
501-1,000 employees
Semiconductor connectivity solutions for cloud AI
No salary listed
San Jose, CA, USA
In Person
 QA & Testing (1) |
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- Deep experience with digital and SerDes high-speed protocols (PCIe Gen5/Gen6, CXL, UCIe, Ethernet/SerDes) and system-level validation methodologies.
- Direct and deep experience working with embedded silicon diagnostic agents.
- Experience working with engineering teams creating product characterization and test plans, test programs, and collaborating with the greater engineering community to obtain and analyze data across process, voltage, and temperature to evaluate semiconductor products.
- Hands-on experience with lab debug tools (protocol analyzers, oscilloscopes, BERTs, error injection frameworks).
- Proficiency in scripting and software development (Python, C/C++, Java, or similar) for diagnostic automation and data analysis.
- Proven ability to analyze complex test data, identify root causes, and implement systemic solutions.
- Familiarity with semiconductor test flows (ATE, system-level test, characterization, production validation).
- Experience with advanced packaging technologies (MCM, 3DIC, optical) and their diagnostic/test challenges.
- Strong communication skills for collaborating across design, product, test, and customer teams.
- Demonstrated ability to influence cross-functional decisions and drive quality improvements at the organizational level.
- Driving Product Quality Engineering: Work with operations, firmware, and other internal engineering teams to drive product quality improvements both as part of NPI activities and volume manufacturing. This role will participate in various NPI engineering reviews to ensure exit criteria are met, new product issues and learnings are addressed, and production issues are driven to root cause. Work with the operations engineering teams to build data systems and infrastructure to eliminate outliers, predict quality trends, and identify product quality opportunities that will improve customer outcomes. Develop signature analysis techniques to identify systemic root causes by leveraging advanced AI and/or ML techniques where appropriate.
- Leading NPI Quality-Related Validation & Issue Debugging: Lead the debugging of complex hardware, firmware, and software issues as part of quality team activities during NPI and high-volume production, leveraging diagnostic hooks and advanced debug tools. Develop and maintain automated diagnostic tools to scale and drive reuse across multiple product families. Partner with operations engineering to improve diagnostic efficiency, reduce overkill/retest, and improve product yield and quality. Integrate diagnostics into silicon lifecycle management, firmware release, and reliability tracking to proactively detect degradation or field reliability risks.
- Interoperability & System-Level Support: Work with field, firmware, and internal engineering teams to ensure interoperability, diagnostic transparency, and robust field debug capability.
- Diagnostic Test Development: Define and drive the deployment of diagnostic test plans, fixtures, tools, and methodologies needed for fault isolation of customer returns in PCIe, CXL, UCIe, Ethernet, and other high-speed switching products. Fan out the most successful tools for broader application in high-volume manufacturing and troubleshooting of NPI (New Products) qualification failures or field application issues.
- Embedded Silicon Agent Champion: Drive the external selection or internal development of embedded silicon agents to monitor temperature, voltage, noise, process, timing, etc., at the block level on-chip. Work with design teams on implementation. Collaborate with validation and design teams to debug these features in the lab during the post-silicon phase. Partner with firmware teams to leverage these features for real-time adaptive behavior. Partner with software teams to process the data and create accessible and actionable diagnostic conclusions.
- Design DFT Review: Work with design, operations engineering, and system validation teams to drive early Design-for-Testability (DFT) and diagnostic capabilities with design and product engineering teams. Coordinate block-by-block-level reviews to ensure no gaps in coverage and that all prior lessons learned are applied.
- Advanced Packaging Diagnostics: Develop diagnostic methodologies for MCM, 3DIC, and optical interconnect packages, including die-to-die and heterogeneous integration interfaces needed to diagnose, isolate, and ensure high-quality products.
- Minimum of 5 years of experience leading a high-caliber product engineering team.
- Minimum of 10 years within a product or diagnostics engineering team with successful deployment of semiconductor devices into production.
- Strong academic/technical background in electrical engineering; Bachelor’s required, Master’s preferred. Experience with diagnostic firmware and test development methodologies.
- Knowledge of advanced techniques for anomaly detection in diagnostic/test data.
- Track record of leadership in new product introduction (NPI) for complex, high-speed semiconductor products.
Astera Labs provides semiconductor-based connectivity solutions to boost cloud and AI infrastructure. Its products include PCIe, CXL, and Ethernet connectivity ICs and adapters that enable high-speed data transfer between processors, memory, and accelerators. These solutions help alleviate the memory wall by improving memory and I/O bandwidth, enabling faster communication within data centers supporting Generative AI workloads. The company differentiates itself by specializing in memory-centric, high-speed interconnects for cloud AI architectures and by targeting data centers and AI infrastructure customers with a portfolio of PCIe, CXL, and Ethernet products, rather than broad consumer-focused offerings. Astera Labs aims to expand its leadership in the global cloud AI market through continued development and deployment of its connectivity solutions, growing its market share and partnerships in data centers and AI workloads.
Company Size
501-1,000
Company Stage
IPO
Headquarters
Santa Clara, California
Founded
2017
Simplify's Take
What believers are saying
- Q1 2026 revenue hit $308 million, up 93% YoY, with PCIe 6 over one-third of sales.
- Scorpio fabric switches ramp to largest revenue by 2026 end, targeting $1,000 per XPU.
- XScale Photonics acquisition drives optical interconnect volumes in 2027.
What critics are saying
- Nvidia NVSwitch 6 triples Scorpio X bandwidth, locking hyperscalers into NVLink by Q4 2026.
- Broadcom Tomahawk 6 commoditizes switches, eroding Scorpio pricing from Q2 2027.
- Nvidia NVLink Fusion sidelines PCIe switches for AMD/Intel GPUs by Q4 2026.
What makes Astera Labs unique
- Astera Labs pioneers PCIe 6.0 Scorpio X switches with 5.12 TB/s bandwidth for rack-scale AI.
- COSMOS software suite enables real-time telemetry across switches, cables, and optics.
- Aries retimers and Taurus controllers solve memory wall in PCIe/CXL/Ethernet connectivity.
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Benefits
401(k) Retirement Plan
Flexible Work Hours
Growth & Insights and Company News
6 month growth
↓ -4%1 year growth
↓ -3%2 year growth
↑ 0%Astera Labs has raised $120 million in a Series C round, valuing the semiconductor connectivity solutions provider at $1.45 billion. Ribbit Capital led the investment, with participation from Sequoia, Kleiner Perkins, and new backer Emerson Collective. The company reported fourth-quarter revenue of $270.6 million, up 17% sequentially and 92% year-over-year. Full-year 2025 revenue reached $852.5 million, a 115% increase from 2024. Non-GAAP earnings per share of $0.58 exceeded consensus estimates by 35%. Astera Labs designs connectivity solutions for cloud and AI infrastructure, with strong demand for its Taurus PCIe/CXL products and Scorpio switchable fabric solutions. The company projects a $25 billion addressable market over five years. Its shares traded at $112.47 as of 27 March, with 52 hedge funds holding positions.
Insiders are showing confidence in several high-growth US companies through significant ownership stakes. The American market has climbed 3.5% over the past week and 31% over the year, with earnings forecast to grow 16% annually. AppLovin Corporation, with a $130.31 billion market cap, has demonstrated strong performance with earnings rising 116.3% over the past year. Revenue is expected to grow 21% annually, outpacing the broader market. The company recently completed a $4.59 billion buyback programme, though it faces high debt levels and share price volatility. Tesla, valued at approximately $1.35 trillion, generates revenue primarily from automotive operations ($82.06 billion) and energy generation and storage ($12.77 billion), with revenue forecast to grow 16.4% annually. High insider ownership often signals management's confidence in future prospects.
Symbotic, Fastly and Astera Labs are positioned to capitalise on AI's growth despite receiving less attention than tech giants like Nvidia and Meta Platforms. Symbotic provides AI-powered warehouse automation and reported a 29% year-over-year revenue increase to $630 million in its fiscal first quarter. The company turned profitable with $13 million net income, reversing a $17 million loss from the previous year. It has a multi-year agreement with Walmart to deploy systems across all 42 distribution centres. Fastly delivers fast and secure online experiences, benefiting from increased AI bot traffic scouring the internet. The global AI-powered robotics market is forecast to expand from $7.5 billion in 2026 to $60.7 billion by 2034, providing a tailwind for these smaller AI companies.
Astera Labs reported strong fourth-quarter results and announced a $6.50 billion warrant agreement with Amazon to expand AI infrastructure partnerships. However, management disclosed an expected 200-basis-point gross margin headwind from module-heavy product mix and the Amazon warrant, reframing near-term profitability expectations. The Amazon deal strengthens Astera Labs' position in AI data centre connectivity, reinforcing demand for its Scorpio switches and COSMOS software as hyperscale deployments expand. Yet it also highlights customer concentration risks and margin pressure that investors must now factor into their valuations. The company's narrative projects $1.5 billion revenue and $393.5 million earnings by 2028, requiring 34.1% annual revenue growth. Cautious analysts note hyperscaler bargaining power could weigh more heavily on margins than consensus expects, particularly given Astera Labs' concentrated customer base.
Artisan Mid Cap Fund has initiated a position in Astera Labs, a fabless semiconductor company providing connectivity chips for data centres, according to its fourth-quarter 2025 investor letter. The fund took advantage of a recent share price pullback to establish what it calls a "Garden" position. Astera Labs manufactures chips that address data, network and memory bandwidth bottlenecks in data centres, helping modern GPUs and CPUs operate at full performance. The company also enables communication across different chip types, supporting the industry's shift towards heterogeneous computing. The fund believes Astera Labs has strong long-term growth prospects driven by continued cloud expansion and rising AI demand. As of 20 February 2026, Astera Labs shares traded at $129.68, with a market capitalisation of $22.073 billion.