SoC Logic Design Engineer

Job Details:

Job Description:

Altera is seeking an experienced SoC Logic Design Engineer to develop and integrate logic design, register transfer level (RTL) coding, and simulation for complex SoC designs. This role involves working on integrating IP blocks and subsystems into a full-chip SoC or discrete component design, while ensuring the highest quality standards in logic design, power, performance, and area optimization.

Key Responsibilities:

• Develop RTL designs for SoC integration, ensuring efficient and optimized logic implementation.

• Participate in defining architecture and microarchitecture features of designated blocks.

• Conduct thorough quality checks across various aspects of logic design, including RTL validation, timing, and power convergence.

• Apply advanced strategies, tools, and methods to optimize RTL for power, performance, area, and timing goals.

• Ensure verification plan and implementation correctly validate design features.

• Identify and resolve RTL issues to maintain design integrity and compliance with security best practices.

• Work closely with IP providers to integrate and validate IPs at the SoC level.

• Ensure smooth IP-SoC handoff through rigorous quality assurance compliance.

Salary Range

Our compensation reflects the cost of labor within the US market. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$181,100K - 289,300K

Qualifications:

• Minimum 7 years of experience in integrating ARM advanced cores and related ARM IP.

• Strong expertise in coherent interconnect design and integration.

• Proven experience as an SoC integrator, handling complex SoC-level integration tasks.

• Demonstrated experience as a lead micro-architect in SoC design.

• Knowledge of Design for Test (DFT), physical design, and verification methodologies.

• Proficiency in static timing analysis and optimization.

• Strong understanding of security best practices in hardware design.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

Austin, Texas, United States

Additional Locations:

San Jose, California, United States

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.