Facebook pixel

Mid-Level Asic Fpga Development and Verification Engineer
Posted on 4/12/2022
INACTIVE
Locations
United States
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
C/C++/C#
Git
Java
Linux/Unix
Perl
Objective-C
Ruby
Python
Writing
Requirements
  • Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry
  • Five (5) or more years of work and/or educational experience in digital ASIC/FPGA design and verification
  • Three (3) or more years of work experience using Verliog or SystemVerilog
Responsibilities
  • Apply understanding of system requirements to architect block level design specifications
  • Prepare detailed design documentation
  • HDL coding, logical equivalency checking, static timing analysis, CDC, linting
  • Integration of third-party IP
  • Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts: Inheritance, Polymorphism, etc
  • Develop Functional Coverage Models and closing Code Coverage
Desired Qualifications
  • Bachelor's degree and 7 or more years' experience in digital ASIC/FPGA design and verification, Master's degree with 5 or more years' experience in digital design/verification, or PhD degree with 2 or more years' experience in digital design/verification
  • Work experience writing Universal Verification Methodology (UVM) sequences and virtual sequences
  • Work experience using Linux or Unix terminal commands
  • Experience using scripting languages: Make, Perl, Python, shell scripts, etc
  • Experience using Revision Control Systems: Subversion (SVN), CVS, Git
  • Work experience writing requirements specification documents
  • Work experience writing architectural design documents (micro-architecture documents with timing diagrams, detailed design blocks, etc.)
  • Work experience performing RTL synthesis
  • Work experience performing Static Timing Analysis and correcting timing violations
  • Work experience simulating a digital design using hardware verification languages: SystemVerilog and SystemVerilog Assertions
  • Work experience using Object Oriented Programming concepts: Inheritance, Polymorphism, etc
  • Work experience using Universal Verification Methodology (UVM): Experience creating drivers, monitors, predictors, and scoreboards
  • Work experience creating a self-checking simulation test benches from scratch
  • Educational or work experience using object oriented programming (OOP), e.g. Java, Python, Ruby, C++, Objective-C, Visual Basic .NET, Smalltalk, Curl, Delphi, Eiffel, SystemVerilog
The Boeing Company
Company mission
Boeing Company manufactures and sells aircraft, rotorcraft, rockets, and satellites and provides product leasing and support services.