Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

You will join our growing Global Advanced Technology Enablement team that is specialized in driving technology development across Samsung System LSI business. We engage with Foundry partners from the very early phase to thoroughly explore target technology for next-generation SoC products.

Samsung System LSI values the strategic importance of DTCO/TE activities, especially for advanced technology beyond 5nm nodes. Our goal is to maximize Samsung LSI’s product benefits, often measured by PPA, Silicon Reliability, and design TAT. As a key member of the team, you will join us in driving Foundry/EDA/Foundation IP (FIP)-Development to unlock technology potential, which is key towards our business success.

• You will collaborate on DTCO activity from early TD up to tape-out and revision.
• You are passionate about driving Foundation IP (FIP) Architecture exploration for new technology. This includes coordinating with the global FIP design team (both in-house and Foundry).
• You are a domain expert in one or more technical areas, such as Advanced Methodology development, ranging from Physical Design (P&R), transistor-level/circuit  Layout, Signoff, Electrical/Physical Verification up to DFM. You will help our team coordinate with global design methodology teams and will often directly drive global R&D teams from various EDA vendors.
• You are an innovator. You thrive on driving future-oriented changes and generating creative perspectives and solutions. You bring fresh ideas to challenge past practices, approaches, and old ways of thinking to introduce new innovation opportunities.  
• You are skilled at driving cross-company collaboration with a global perspective by creating synergetic ways of working using effective communications and proactive partnership

Skills and Qualifications

• 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+  years of experience with a Master’s Degree, or 2+ years of experience with a PhD
• Technology Enablement (TE) and DTCO experience at advanced technology nodes (below 5nm). The activity includes technology, logic and memory cell architecture exploration. Multiple-Foundry experience is a plus.
• Foundation IP (both Library Cell and SRAM Memory) design experience up to MTO and post-Silicon activity.
• Experienced in Physical Design (e.g., Synthesis and P&R), PDN design, library exploration, EDA tools, etc. EDA interfacing experience is a plus.

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