Responsibilities

• Develop PDV methodology and infrastructure to enable the verification flow of large SoCs across DRC, LVS, ESD.
• Drive convergence across analysis types at full chip level and sub blocks.
• Perform full chip integration and run the complete suite of physical verification checks
• Provide guidance to the implementation teams throughout the project to enable early convergence and final closure
• Interface with various internal and external design teams to ensure the high quality of their deliverables and successful integration
• Work with the package and floorplan teams to define padring and bump map design
• Collaborate with our technology team to define flows and integrate foundry PDK data
• Manage a team of engineers to deliver PDV convergence to meet or exceed program milestones.

Requirements

• Deep understanding of the challenges associated with advanced process nodes (7nm and below).
• More than 10 years experience in managing and driving full chip convergence for high end chip designs using advanced process nodes.
• Hands-on experience with auditing rule decks and settings to drive convergence.
• Hands-on experience in closure and tapeout of large hierarchical designs.
• Experience with industry standard physical verification tools (Calibre, Pegasus)
• Strong scripting skills in tcl and python
• Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
• Self starter and highly motivated
• Ability to work cross-functionally with various teams and be productive under aggressive schedules
• Good written and verbal communication skills.