At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is the leader in hardware emulation-acceleration technologies and products. Looking for a talented ASIC and FPGA designer early in his or her career interested in diverse challenging opportunities to develop complex and creative architectures and designer solutions to difficult problems. This position is located in our San Jose headquarter office, reports to the Sr. Engineering Manager Logic/Microarchitecture Design, and works in a growing, dynamic organization.
Our emulation-acceleration system platform is the most advanced industry-leading configurable scalable system, generation after generation, used in labs and datacenters. At the heart of these systems are a multitude of interconnected highly complex high-performance computing (HPC) devices based on a proprietary Boolean processor architecture. This is a role on the core technology team responsible for research and development of these ASIC engines and how they work as a system to reprogrammably emulate customers’ logic circuitry up to multi-billion-gate systems.
Key responsibilities
Develop and unit-test ASIC blocks and components of subsystems (in some cases involving FPGAs) from concept to productization, including:
o Considering and reporting results for key design metrics, such as area, power, and performance
o Interfacing to third-party IP
o Suggesting and executing your portion of development, bringup and test plans
o Developing and maintaining internal specifications
o Writing RTL (Verilog) and unit simulation tests
o Evaluating synthesis and timing analysis results
o Working closely with assigned members of the verification team
o Collaborating with firmware teams during specification and integration
o Working with system and design validation teams during bringup and design validation test phases.
o Supporting diagnostic and test teams to achieve fault isolation, and function and robustness test
· Work in small dynamically evolving teams for subprojects involving internal and external resources.
· Learn from senior team members to become expert in several areas, processes and flows.
Qualifications
· Degree in Electrical or Computer Engineering, graduate level or compensating experience.
· Experience in basic projects in logic, ASIC, VLSI, and FPGA development
· Comfortable in Verilog and SystemVerilog for development of simple and complex logic systems.
· Aware of ASIC design flow. Experience with some frontend design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis. Exposure to backend tools a plus.
· Exposure in to some major IP and protocols, such as SERDES, PCIe and DDR4
· Familiar with the theory behind DFT, BIST, other DFx methologies
· Good scripting skills (e.g. Python, Perl, TCL).
· Familiarity with verification methodologies and emulation or prototyping experience helpful.
· Problem-solving and debug skills. Can decide the path to isolate a problem and can infer what a result means.
· Energetic. Self-driven. Good communication, organization, analytical, presentation and people skills.
· Does not wish to be confined to a small focused role. Driven to understand the big picture. Can easily switch gears and take on new and diverse tasks.
· Willing to learn and develop as an engineer.
Ken Smith | Sr. Recruiter, Talent Acquisition | Let’s Connect
P: 503. 544. 7954| [email protected] | Cadence Careers
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