Job Description

SEAKR is seeking a Verification Engineer who is responsible for developing verification and simulation strategies, creating a digital test plan and providing coverage metrics. 

• The Engineer is responsible for the construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology), and performing and evaluating regression tests for a design under test. 
• The candidate must be able to extract and derive test requirements and sequences for an interface or interfaces based on available design documentation and requirements. 
• Ability to architect and construct full test environments for simple devices using UVM, including coverage, is a plus.
• Ability to analyze and write System Verilog is required. 
• The candidate shall be capable of diagnosing sophisticated test failures and filing results and be capable of analyzing code coverage to adjust agent sequence behavior. 
• Ability to analyze Verilog RTL to diagnose test failures is required. 
• Ability to diagnose VHDL RTL is a plus. 
• Ability to perform and evaluate regression tests for a design under test is a plus. 
• Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting is required. 
• Must be able to work effectively under pressure to meet tight deadlines. 
• Experience verifying DSP related designs is a plus.

Qualifications

• A Bachelors degree in Electrical Engineering or Computer Science. A Master’s Degree is preferred.
• 0 to 3 years of verification engineering experience are required.