ASIC Engineer

• Work as part of the team that delivers coherent fabric interconnect solutions.
• Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
• Perform RTL development (SystemVerilog), debug functional/performance simulations.
• Perform RTL quality checks including Lint, CDC, Synthesis, Unified Power Format (UPF) checks.
• Participate in synthesis, timing/power estimation and field-programmable gate array (FPGA)/silicon bring-up.

Minimum qualifications:

• Bachelor’s degree in Electrical or Computer Engineering or equivalent practical experience.
• 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology.
• 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture.
• Experience with a coding language like Python or Perl.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.
• 6 years of industry experience with Intellectual Property (IP) design.
• Experience with methodologies for Register-Transfer Level (RTL) quality checks (e.g., Lint, CDC, RDC).
• Experience with methodologies for low power estimation, timing closure, synthesis.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Bachelor’s degree in Electrical or Computer Engineering or equivalent practical experience.
• 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology.
• 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture.
• Experience with a coding language like Python or Perl.