Silicon Design Verification Engineer

• Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
• Identify and write all types of coverage measures for stimulus and corner-cases.
  
• Debug tests with design engineers to deliver functionally correct design blocks.
  
• Measure to identify verification holes and to show progress towards tape-out.
  
• Create a constrained-random verification environment using SystemVerilog and Universal verification methodology (UVM).
  

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
  
• 4 years of experience with verification methodology such as Universal verification methodology (UVM).
  
• 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
  
• Experience with SystemVerilog, SVA, and functional coverage.
  

Preferred qualifications:

• Master's degree in Electrical Engineering or a related field.
  
• Experience with industry-standard simulators, revision control systems, and regression systems.
  
• Experience with the full verification life cycle.
  
• Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units.
  
• Excellent problem solving and communication skills.
  

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will own the full verification life cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
  
• 4 years of experience with verification methodology such as Universal verification methodology (UVM).
  
• 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
  
• Experience with SystemVerilog, SVA, and functional coverage.