New College Grad

Job Description

The Memory Technology Group is at the core of the Legacy SanDisk Engineering Organization which Western Digital owns. We are building a cutting-edge 3D NAND Flash memory in our multi-billion dollars Fab. Our memory provides performance, power, and endurance at a lower cost without forgoing quality. 

We are looking for a highly motivated New College Graduate to join the Memory Technology Design team in Milpitas, CA. The candidate will be responsible for all aspects of digital design in advanced 3D NAND Flash memory, focusing on micro architecture, RTL design, verification, logic synthesis, and static timing analysis to deliver a design meeting target power, performance and area goals.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design for testing (DFT), synthesis, timing analysis and closure
• Balance design trade-offs with modularity, scalability, power, area, and performance.
• Interface with internal and external teams/customers to drive necessary technical specifications and features based on individual requirements
• Participate in silicon debugging and support post-silicon validation

This is a great opportunity for a results-oriented, entrepreneurial individual who knows how to work with non-volatile memory world-class engineers and has a great track record for delivering innovative results. You will need to think creatively about the memory as we do take pride in our craftsmanship. We do work together with all engineering teams to identify and execute on the most disciplined way. Your success will be measured by your ability to build great designs that deliver innovation that unlock revenue opportunities for the company.

Qualifications

REQUIRED:

• Master’s degree in electrical engineering, computer engineering, or related engineering field with a graduation date before July 2025.
  The expected start date for this position is in July or August 2025.
• Knowledge of the entire Logic Design Flow (from RTL to GDSII) is required, (including Micro architecture, Verilog RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion, place-and-route, clock tree synthesis, extraction, timing closure and signoff, physical verification)
• Knowledge of logic design principles along with timing and power implications
• Good critical thinking, problem-solving, and presentation skills are required
• Excellent communication (written and verbal) and interpersonal skills with the ability to work in a cross-functional team setting

PREFERRED:

• Industry or academic experience in digital circuit design or RTL design is preferred, especially from full-time or internship experience
• Working knowledge on C, C++, Python is preferred
• Decent knowledge in Memory Design concept is preferred