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Summer Intern
Foundry
Confirmed live in the last 24 hours
Locations
San Jose, CA, USA
Experience Level
Intern
Requirements
  • Understanding of ASIC design flow. Good knowledge of physical design automation flow, Tcl or Perl scripting , MS Office
  • VLSI design experience. RTL design using Verilog HDL is preferred
  • Good trouble-shooting skills
  • BS or above
  • MS or PhD candidate preferred
Cadence Design Systems

5,001-10,000 employees

Cadence Design Systems is a computational software company.
Company Overview
Cadence Design Systems is a computational software company.