Senior ASIC Design Engineer

As a member of our digital logic interconnect design team, you will be responsible for implementing logic for our next-generation GPU’s and SOCs which enable high-performance interconnect of multi-GPU/CPU/DPU system topologies for autonomous machines, Cloud and Data Centers, Deep learning, High-Performance Computing, Gaming, and Entertainment solutions. Tasks will include micro-architectural definition, RTL coding, logic debug, timing closure, power optimization and verification support. The ideal candidate will have 10+ years of direct experience with PCIE Physical/Datal-Link Layer or other industry standard protocols like CXL, AXI, CHI, UCIe USB, SATA.

What you’ll be doing:

• micro architecting the next generation of PCIE PL and DL

• implementing readable, high-performance, area and power efficient RTL to achieve design targets, including upcoming performance, adaptability, and safety industry standards

• collaborating with architects, external partners, software engineers and circuit designers to deliver best in class IP

• partnering with our Physical Design team on partitioning, floorplanning and timing closure

• providing design documentation, triaging and debugging functional and performance bugs, integration and infrastructure support and development

What we need to see:

• Bachelors Degree in EE, CS or CE or equivalent experience

• 8+ years of relevant experience or an Advanced Degree with equivalent experience

• 5+ years experience in coding PCIE PL/DL logic or lower layers of the OSI stack in general

• in-depth understanding of physical design

• strong working knowledge of Verilog or System Verilog

• strong collaboration and communication skills

• able to lead junior engineers and assist management with task assignments, scheduling, and other project management tasks

Ways to stand out from the crowd:

• good knowledge of PCIe PL/DL sub blocks such as: data scrambling, packet framing, NRZ/PAM4 encoding, equalization, TLPs/DLLPs, LTSSM, power states, errors, etc

• knowledge of alternate protocol negotiation, CXL/UCIe would be an added advantage

• experience in handling post-silicon bringup, and good understanding of signal integrity concepts

• understanding of firmware/driver structures and their interaction with HW

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come join our design team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field.

#LI-Hybrid

The base salary range is 168,000 USD - 310,500 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.