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Full-Time

Principal Verification Engineer I

Posted on 1/15/2024

CesiumAstro

CesiumAstro

51-200 employees

Develops phased array communication payloads

Hardware
Aerospace

Senior

Austin, TX, USA

Category
Hardware Engineering
Hardware Validation & Testing
System Hardware Engineering
Required Skills
Verilog
Python
MATLAB
VHDL
FPGA
Linux/Unix
Requirements
  • A Bachelor of Science (BS) or Master of Science (MS) degree in Computer Science, Electrical Engineering, or Computer Engineering.
  • Minimum of 9 years of industry experience in verification and automation.
  • Expert-level knowledge of FPGA digital design verification techniques including VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional analysis, QEMU and VIP.
  • Expert-level knowledge of digital design automation infrastructure, including CI, regression testing and HIL testing.
  • Advanced-level knowledge of Linux.
  • Advanced-level knowledge of vendor-provided FPGA development tools with a focus on Xilinx tools.
  • Desire and ability to train and mentor while maintaining a positive and productive attitude.
Responsibilities
  • Lead the evaluation and technical implementation of FPGA and digital design simulation, verification and emulation infrastructure.
  • Lead the development, maintenance and phased deployment of continuous integration and regression testing infrastructure.
  • Develop state-of-the-art UVMf-based top-level and module-level testbenches using block-to-top best practices for reusability, including both control and data plane stimulation using VIP & System Verilog DPI-C integration with existing MATLAB and Python numerical models.
  • Lead the development of reusable custom VIP modules.
  • Work closely with the engineering and senior leadership teams to train and mentor engineers at all experience levels on UVMf testbench usage and modern approaches to FPGA/digital design.
  • Work with the modeling and scientific staff to implement DPI-C dataplane verification interfaces into existing MATLAB and Python models.
  • Regularly communicate and present on the current state of verification in the industry, and at the company.
  • Continually evaluate current processes regarding FPGA and digital design with a focus on Xilinx TLM models and QEMU-RP integration.
  • Work closely with vendors to define requirements of future simulation model deliverables.
  • Maintain up-to-date knowledge of industry best-practices regarding FPGA and digital design methodologies.
  • Work closely with the engineering leadership team to evaluate and non-disruptively implement process improvements.

CesiumAstro specializes in developing cutting-edge phased array communication payloads for both airborne and space platforms, offering mission-ready solutions tailored for high throughput communication needs utilizing modular hardware and software. This focus on complex engineering solutions and a modular approach positions the company well within the aerospace industry. The collaborative and technology-driven work environment, underlain by a dedication to innovative payload solutions, makes it a promising workplace for professionals eager to engage with top-tier aerospace technologies and contribute to significant industry advancements.

Company Stage

N/A

Total Funding

$120.2M

Headquarters

Austin, Texas

Founded

2017

Growth & Insights
Headcount

6 month growth

22%

1 year growth

41%

2 year growth

92%
INACTIVE