Memory Subsystem Intern
Posted on 3/29/2024
Rivos

201-500 employees

High performance CPUs & RISC-V
Company Overview
Rivos is a startup in stealth-mode.
Hardware

Company Stage

Series A

Total Funding

$120M

Founded

2021

Headquarters

Mountain View, California

Growth & Insights
Headcount

6 month growth

0%

1 year growth

9%

2 year growth

41%
Locations
Santa Clara, CA, USA
Experience Level
Intern
Desired Skills
Verilog
Python
CategoriesNew
Hardware Engineering
Computer Hardware Engineering
System Hardware Engineering
Requirements
  • Knowledge in memory subsystem design, cache memory, LPDDR/DDR/HBM/CXL memory
  • Knowledge and experience with common LLM (Large Language Model) workloads
  • Proficiency in System Verilog, C or C++, scripting languages such as Python
  • Experience with high-level simulators for performance or power estimation is a plus
  • Knowledge in server-class GPU/ML architecture is a plus
Responsibilities
  • Responsible for an analytical model of LLM inference and training memory usage
  • Responsible for running the performance simulation to extract the workload's memory footprint and bandwidth requirement
  • Responsible for identifying memory subsystem capacity or bandwidth bottlenecks and improve the performance and energy efficiency