Formal Verification Engineer

Responsibilities

• Drive Formal Verification Methodology on multiple components inside Custom AI Inference IP. This is not limited to creating and executing verification plan, debugging issues and coverage closure.
• Evaluating various formal verification technologies and flows.

Preferred Skills & Experience

• Knowledge of a property checking language such as SystemVerilog Assertion (SVA) and understanding of HDL languages such as SystemVerilog or Verilog.
• Familiar with AMBA protocols such as AHB, APB and AXI.
• Knowledge of Computer Architecture. Familiar with RISC-V ISA.
• Able to use scripting languages such as Python.
• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.
• 3+ years’ experience with hands-on design verification with 2+ years in formal verification.

What are some of the perks that you will receive being part of Untether AI? Aligned to Untether’s philosophy, our employees enjoy the same perks, regardless of role or level. In part, these include:

• 20 vacation days
• Strong health and extended health benefits
• Unlimited sick days
• Stock options
• Building chips and software that will change the world

Thinking about applying?

• We’re a pretty welcoming bunch of people. If we’ve piqued your interest, you’re passionate about the same things we are but you aren’t sure if you check all the boxes, please apply anyway. We’re a great place to work, an even better place to learn and we focus on both capability and potential!
• Besides being a pretty friendly group, we’re also pretty diverse - ethnically, experientially and in our physical and mental abilities. If you are someone who needs accommodation during the interview process and/or in the workplace, please send a note along with your resume to [email protected] and we’ll be in touch.