Full-Time

CPU Microarchitecture & Logic Design

Full time

Confirmed live in the last 24 hours

Rivos

Rivos

201-500 employees

High performance RISC-V computing solutions

Hardware

Mid

Santa Clara, CA, USA

Required Skills
Verilog
Python
Perl
Requirements
  • Thorough knowledge of microprocessor architecture and microarchitecture in memory management, load/store execution, cache and memory subsystems, bus interface, debug features, and power management
  • Knowledge of System Verilog
  • Experience with simulators and waveform debugging tools
  • Knowledge of logic design principles along with timing and power implications
  • Understanding of low power microarchitecture techniques
  • Understanding of high performance techniques and trade-offs in a CPU microarchitecture
  • Experience in C or C++ programming
  • Experience using an interpretive language such as Perl or Python
Responsibilities
  • Microarchitecture development and specification
  • Development, assessment, and refinement of RTL design
  • Validation support test bench development and simulation
  • Performance exploration and correlation
  • Design delivery work with multi-functional engineering team to implement and validate physical design

Rivos provides a compelling work environment for those keen on contributing to leading-edge computing solutions in the enterprise sector. The company is a specialist in leveraging high-performance RISC-V systems, positioning it as a key player in the advanced computing niche. Working here exposes employees to cutting-edge technology and significant industry challenges, nurturing a culture of innovation and technical excellence.

Company Stage

Series A

Total Funding

$250M

Headquarters

Santa Clara, California

Founded

2021

Growth & Insights
Headcount

6 month growth

4%

1 year growth

0%

2 year growth

47%