Principal DFT Engineer
Confirmed live in the last 24 hours
Irvine, CA, USA
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 10+ years of experience working with ASICs
- 10+ years of experience in scan insertion and DFT setup, integration and validation
- Understanding of ASIC design flow, methodologies, physical design, and verification
- RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT
- Ability to solve complex problems including clock domain crossings and power optimization
- Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
- Familiar with advanced silicon process and technology nodes for high speed and low power consumption
- Experience with high reliability design and implementations
- Excellent scripting skills (csh/bash, Perl, Python etc.)
- Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
- Ability to work in a dynamic environment with changing needs and requirements
- Team-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basis
- Enjoys being challenged and learning new skills
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- Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
- Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
- Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage
- Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals
- Run and debug non-timing and SDF annotated gate level simulations
- Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation
- Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon
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