Member of Technical Staff Ref
Posted on 2/13/2024
INACTIVE
Rivos

201-500 employees

High performance CPUs & RISC-V
Company Overview
Rivos is a startup in stealth-mode.
Hardware

Company Stage

Series A

Total Funding

$120M

Founded

2021

Headquarters

Mountain View, California

Growth & Insights
Headcount

6 month growth

0%

1 year growth

11%

2 year growth

40%
Locations
Austin, TX, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
Verilog
VHDL
CategoriesNew
Hardware Engineering
Requirements
  • Master’s or foreign equivalent in Computer Engineering, Electronics Engineering, or a related field
  • 2 years of experience in job offered or related occupation
  • At least 1 year of prior work experience in SystemVerilog, Verilog, and SystemVerilog Assertions
  • At least 1 year of prior work experience in computer architecture and logic design principles
  • At least 1 year of prior work experience in timing and area tradeoffs in a CPU microarchitecture
  • At least 1 year of prior work experience in RTL simulation and waveform debugging tools
  • At least 1 year of prior work experience in low-power techniques including clock gating and power gating
Responsibilities
  • Develop microarchitecture specifications and own the RTL development for CPU features
  • Debug complex failure modes involving timeouts, data corruption, and incorrect circuit operation
  • Collaborate with software and architecture teams to identify performance limiting aspects of current software and hardware interactions
  • Model, design, simulate, test and implement electronic systems using System Verilog HDL
  • Deliver a design which meets functional, performance, power, and area requirements