Principal Engineer
Cache Coherency Subsystem Verification
Posted on 10/11/2023
INACTIVE
Ampere

1,001-5,000 employees

Designs Cloud Native Processors for hyperscale cloud and edge computing
Company Overview
Ampere Computing, a semiconductor company, is a pioneer in designing Cloud Native Processors, which are instrumental in shaping the future of hyperscale cloud and edge computing. The company's modern 64-bit Arm server-based architecture, known for its superior cloud performance, power efficiency, and scalability, is highly sought after by leading cloud service providers to expedite the delivery of cloud computing applications. By switching to Ampere's processors, businesses can achieve significant cost savings and maintain a competitive edge through optimal performance.
Hardware

Company Stage

Series C

Total Funding

$766M

Founded

2017

Headquarters

Santa Clara, California

Growth & Insights
Headcount

6 month growth

5%

1 year growth

24%

2 year growth

62%
Locations
Austin, TX, USA • Santa Clara, CA, USA • Durham, NC, USA • Portland, OR...
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
Python
Perl
FPGA
CategoriesNew
Software Engineering
Requirements
  • Minimum MS & 6 years or BS & 8 years of IP and subsystem design verification experience
  • Solid understanding of high-performance multi-core processor architecture and microarchitecture, especially OOO memory and cache coherency protocols
  • Prior experience in verifying Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols or other high performance interconnect protocols
  • Experienced in building new verification test benches using industry standard languages like System Verilog, UVM/OVM
  • Programming experience in 1 or more languages common to the industry (e.g., C, C++)
  • Experience in automating design/verification tasks using perl/python or other scripting languages
  • Knowledge of ARM or x86 memory architecture and assembly language programming
  • Prior experience in leading design verification efforts and strong verification mindset with excellent attention to detail
  • Technical leadership skills like ability to articulate vision, inspire the team, plan, and organize team’s work, make difficult decisions
  • Strong analytical and problem skills and able to communicate technical concepts, status, and issues clearly
  • Previous experience in CPU/core design verification is preferred
  • Previous experience in emulation, FPGA and post-silicon validation is preferred
  • BS/MS Electrical Engineering or Computer Engineering
Responsibilities
  • Strategize and execute cache coherency subsystem verification efforts across verification platforms
  • Review architecture and microarchitecture specs and influence design/microarchitecture decisions
  • Define verification strategy and test plans for cache coherency subsystem verification
  • Architect and lead development of verification collateral including test benches, random test generators and checkers
  • Lead and contribute to day-to-day execution of all verification activities to meet tape out quality requirements
  • Define post-si validation plans and debug post-silicon system level failures
  • Mentor/guide the work of other engineers to achieve project goals
Desired Qualifications
  • Previous experience in CPU/core design verification
  • Previous experience in emulation, FPGA and post-silicon validation