Job Details:

Job Description: 

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

The DCAI and Silicon Eng Team (DASE) deliver leadership Xeon products to cloud and datacenter customers through development of industry leading x86 core and differentiated IPs that enhances product performance and competitiveness in both Xeon and AI platforms. IP design group within DCAI designs Coherent Fabric IP, Memory controller, NOC, PCIE and many fundamental building blocks for the Xeon server SOCs.
 

Who You Are

We are seeking an experienced Senior Micro Architect to design, develop, and implement advanced memory coherency fabric systems for next-generation data center and AI chips. This role requires a unique blend of architectural expertise and hands-on RTL coding skills to bring cutting-edge designs to life. The ideal candidate will have a deep understanding of memory subsystem architecture, interconnect protocols, and coherency mechanisms, coupled with a proven ability to implement these designs at the RTL level.

Your responsibilities include but not limited to:

• Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.

• Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks.

• Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs.

• Work closely with verification teams to create test plans and debug issues arising during pre-silicon validation.

• Collaborate with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems.

• Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases.

• Mentor junior engineers and contribute to technical reviews and design documentation.

• Stay updated with emerging technologies and trends in memory subsystems, coherency protocols, and AI/ML hardware.

• Strong problem-solving and debugging skills.

• Excellent communication and collaboration abilities.

• Ability to manage and prioritize multiple tasks effectively.

Qualifications:

Minimum Qualifications

• Graduate of Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field with at least 4+ years’ experience in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding OR;

• Graduate of Master’s Degree in Electrical Engineering, Computer Engineering, or a related field with at least 3+ years’ experience in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding OR;

• PhD in Electrical Engineering, Computer Engineering, or a related field.

• Expertise in memory coherency protocols (e.g., MESI, MOESI, CXL, CCIX, CHI).

• Strong knowledge of interconnect technologies (e.g., AMBA, PCIe, NoC architectures).

• Proven RTL coding experience in Verilog or SystemVerilog.

• Proficiency in simulation tools for performance modeling and analysis.

• Familiarity with physical design implications of memory fabric architectures (timing, power, area).

• Experience with EDA tools for synthesis, linting, and static timing analysis.

Preferred Experience

• Experience with high-bandwidth memory (HBM), DDR, or other advanced memory technologies.

• Knowledge in AI/ML accelerator or data center SoC design.

• Knowledge of scripting languages like Python or TCL for workflow automation.

• Experience with software-hardware co-design for end-to-end system optimization.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Santa Clara

Additional Locations:

US, Massachusetts, Beaver Brook

Business group:

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$144,501.00-$217,311.00

Salaryrangedependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.