Senior ASIC Design Engineer
Confirmed live in the last 24 hours
San Jose, CA, USA
Experience Level
Desired Skills
  • 5+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog
  • Experience in IP integration, specifically CPU IP into SoC
  • Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
  • Familiarity with AMBA/APB/AXI Protocol
  • Familiarity with processor peripheral interfaces like SPI, eMMC
  • MII, GPIO, I2C
  • Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies
  • Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains
  • Interest to explore AI architectures for convolution, transformer and other kinds of workloads
  • Self-starter and highly-motivated to work in a dynamic start-up environment
  • B.S. (M.S. preferred) degree in Electrical or Computer engineering
  • Author micro-architecture specifications and participate in specification and test plan reviews
  • Architect and implement complex RTL designs
  • Scope third party IP requirements and solicit vendors
  • Integrate CPU and other relevant IPs into the CPU sub-system
  • Collaborate with the physical design team to resolve implementation and timing issues and to optimize power
  • Analyze code coverage and provide feedback to the verification team to achieve coverage closure
  • Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab
Desired Qualifications
  • Previous experience with timing closure at high frequencies is a plus

51-200 employees

Realtime object recognition