Responsibilities

• RTL design and Microarchitecture of a high-performance Fabric used in a data center class from-scratch CPU, working closely with the DV and PD team 
• RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure 
• Work with design, test and post silicon validation teams for high quality delivery of the Fabric and Memory Subsystem 
• Evaluate and integrate 3rd party IP components in the design 
• Drive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goals 
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results 
• Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environment 
• Enhance RTL design environment, tools and infrastructure 

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience 
• Strong background and experience with high performance OOO CPU microarchitecture especially with load/store, caches and memory subsystem  
• Experience working on a Fabric for a CPU, GPU based system 
• Knowledge of industry standard protocols such as CHI, AXI, ACE, Tilelink, CMN 
• Architectural understanding of memory ordering, cache coherence protocols, memory consistency, multi-processors and fabric topologies 
• Expertise in logic design and ability to evaluate functional, performance, timing and power for you design 
• Strong experience with hardware description languages (Verilog, VHDL), simulators (VCS, NC, Verilator), Synthesis and Power tools 
• Expertise in microarchitecture definition and specification development 
• Strong problem solving and debug skills across various levels of design hierarchies