Full-Time
Principal Digital Design Engineer
Confirmed live in the last 24 hours
Provides semiconductor-based connectivity solutions
Hardware
Senior
Santa Clara, CA, USA
Required Skills
Python
Requirements
- Strong academic and technical background in electrical engineering
- Bachelor’s degree in EE required, Master’s degree preferred
- 10+ years’ experience in SoC/silicon products for Server, Storage, and/or Networking applications
- Professional attitude with the ability to prioritize tasks and work independently
- Authorized to work in the US
Responsibilities
- Developing micro-architecture and implementation of front-end circuit design
- Knowledge of communication/interface protocols like PCIe, Ethernet, NVMe
- Hands-on design expertise, simulations, synthesis, timing closure, etc.
- Ownership from architecture to GDS, driving designs to production
- Experience with Cadence and/or Synopsys digital design tools/flows
- Design for test (DFT), scan test insertion, UVM based design verification
- Silicon bring-up and debug expertise
- Small-geometry CMOS (≤28nm) design
- Scripting with Python or equivalent programming languages
- Development/support for PCIe or Ethernet Switch products
Astera Labs specializes in semiconductor-based connectivity solutions, including PCIe, CXL, and Ethernet technologies, designed to optimize cloud and AI infrastructure by addressing performance bottlenecks in data-centric systems.
Company Stage
IPO
Total Funding
$739.4M
Headquarters
Santa Clara, California
Founded
2017
Growth & Insights
Headcount