CPU Static Timing Analysis Engineer
Full Time
Confirmed live in the last 24 hours
Austin, TX, USA • Mountain View, CA, USA
Experience Level
  • Hands-on experience in ASIC timing constraints generation and timing closure
  • Expertise and advanced knowledge of industry standard timing EDA tools
  • Deep understanding and experience in timing closure of various functional and test modes
  • Expertise in timing convergence issues associated with deep-sub micron processes (crosstalk delay, noise glitch, POCV, IR-STA) for high performance design
  • Proficient in scripting languages (csh/bash, TCL and Python)
  • Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
  • Self starter and highly motivated
  • Ability to work cross-functionally with various teams and be productive under aggressive schedules
  • PhD, Master's Degree or Bachelor's Degree in EE, EECS or CE
  • Block level and/or full chip timing analysis throughout the life cycle of a project, from early investigation to final implementation and tapeout
  • Develop our timing methodology and infrastructure to support the timing flow from RTL synthesis to PnR and timing closure
  • Develop and maintain key STA checks and associated sign-offs for our CPUs
  • Develop and maintain our Clock-Domain-Crossing check for our CPUs
  • Work with architects and logic designers to generate block and full chip timing constraints
  • Work with system and technology teams to define analysis scenarios and margining strategies
  • Develop and maintain a rigorous and comprehensive signoff methodology to guarantee high quality robust silicon
  • Partner with physical design teams to close and sign off the designs

51-200 employees

High performance CPUs & RISC-V
Company Overview
Rivos is a startup in stealth-mode.