d-Matrix has fundamentally changed the physics of memory-compute integration with our digital in-memory compute (DIMC) engine. The “holy grail” of AI compute has been to break through the memory wall to minimize data movements. We’ve achieved this with a first-of-its-kind DIMC engine. Having secured over $154M, $110M in our Series B offering, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with our chiplets and In-Memory compute approach. We are on track to deliver our first commercial product in 2024. We are poised to meet the energy and performance demands of these Large Language Models.The company has 100+ employees across Silicon Valley, Sydney and Bengaluru.
Our pedigree comes from companies like Microsoft, Broadcom, Inphi, Intel, Texas Instruments, Lucent, MIPS and Wave Computing. Our past successes include building chips for all the cloud hyperscalers globally - Amazon, Facebook, Google, Microsoft, Alibaba, Tencent along with enterprise and mobile operators like China Mobile, Cisco, Nokia, Ciena, Reliance Jio, Verizon, AT&AT. We are recognized leaders in the mixed signal, DSP connectivity space, now applying our skills to next generation AI.
Location:
Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week.
What You Will Do:
Work on chip(s) bring up, Validation and debug of a cutting edge interference accelerator chiplet. It includes -
High speed serial protocol - PCIe Gen5,
High speed memory interface - LPDDR5, and
Die-to-die chiplet interconnect blocks.
Create and execute on test bring up and detailed validation plan as well as test automation (wherever applicable) with the team.
Build tests scripts for host systems to test various validation aspects of high speed interface(s) such as PCIe, and/or LPDDR, and/or D2D.
Work with the team on procuring/acquiring lab equipment.
Collaborate with hardware, software and operations team on various aspects (such as ATE tests, hardware/software debug etc.)
What you will bring:
BS/MS in Electrical/Computer Engineering with 12 to 15+ years industry experience post-Si validation with at least 3-5 years as a lead/manager.
Familiarity with high speed serial protocol (such as PCIe Gen3/4/5) and/or high speed external memory technology (such as LPDDR3/LPDDR4/LPDDR5 and/or high speed I/O standards.
Experienced with PLLs, Si bring up and familiarity with Lab equipment (such as Oscilloscopes, pattern generator, logic analyzer etc)
Excellent debugging verbal and written communication skills
Capable of working effectively across cross functional organizational boundaries.
Leader with a passion for successful products and capable of driving team direction and bring up strategy.
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Equal Opportunity Employment Policy
d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.
d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.
