Facebook pixel

Sr. Full Chip Physical Design Engineer
Silicon Engineering
Confirmed live in the last 24 hours
Locations
Irvine, CA, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
Requirements
  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC top level tapeout and/or physical design flow development experience
  • Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
  • Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.)
  • In-depth knowledge of industry standard EDA tools, understand their capabilities and underlying algorithms
  • Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
  • Strong knowledge of deep sub-micron FinFET technology nodes (7nm and below) design problems and solutions (leakage power, signal integrity, etc.) multi-corner and multimode timing closure, process variations, physical verification methodology and tapeout
  • Familiar with implementation or integration of design blocks using Verilog/System Verilog
  • Experience with clock domain crossings, DFT/Scan/MBIST/LBIST/JTAG/Boundary-scan testing and understanding impacts on physical design flow
  • Experience with high reliability design and implementations
  • Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
  • Must be willing to travel when needed (typically <10%)
  • Willing to work extended hours and weekends to meet critical deadlines, as needed
  • To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here
Responsibilities
  • Perform SOC top level physical design; floor-planning, I/O, bump & RDL (redistribution layer) planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, partition hardening, chip level clock, feedthrough, special interface, and interconnect planning, bus routing, sequential pipeline planning and top level design for testability (DFT) planning
  • Collaborate with chip architects, ASIC engineers, package engineers and block level physical design engineers to drive, chip floorplan reviews and identify area, interconnect, IP integration, and floorplan improvement opportunities
  • Perform chip timing budgeting and constraint pushdown to partition owners
  • Work with static timing analysis, physical verification, electromigration/voltage drop, noise and other signoff teams to achieve closure and tapeout on time
  • Run physical verification at chip level and provide feedback and guidance to block level physical design engineers to fix design rule check/layout versus schematic/antenna/electrical rule check/design for manufacturing violations
  • Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements
SpaceX

10,001+ employees

Designs, manufactures, & launches rockets and spacecrafts
Aerospace
Transportation
Company Overview
SpaceX's mission is to make humanity multiplanetary. The company is working on a next generation of fully reusable launch vehicles that will be the most powerful ever built, capable of carrying humans to Mars and other destinations in the solar system.
Benefits
  • Benefits and Perks - Our employees’ well-being is important to us and essential to our capacity to do extraordinary things. We offer a wide variety of programs to support the health, wellness, and financial security of our employees and their families.
Company Core Values
  • Make History - SpaceX has gained worldwide attention for a series of historic milestones. It is the only private company capable of returning a spacecraft from low-Earth orbit, and in 2012 our Dragon spacecraft became the first commercial spacecraft to deliver cargo to and from the International Space Station. And in 2020, SpaceX became the first private company to take humans there as well.
  • Reusability - SpaceX believes a fully and rapidly reusable rocket is the pivotal breakthrough needed to substantially reduce the cost of space access. The majority of the launch cost comes from building the rocket, which historically has flown only once.
  • Landing - SpaceX’s family of Falcon launch vehicles are the first and only orbital class rockets capable of reflight. Depending on the performance required for the mission, Falcon lands on one of our autonomous spaceport droneships out on the ocean or one of our landing zones near our launch pads.