Senior Member of Technical Staff @ Rivos

INACTIVE

Full-Time

Senior Member of Technical Staff

Posted on 4/3/2024

Rivos

201-500 employees

High performance RISC-V computing solutions

Hardware

Senior

Remote in USA

Required Skills

Python

Perl

Requirements

Master's or foreign equivalent in Electrical Engineering or related field
3 years of experience in job offered or related occupation
At least 1 year of prior work experience in ASIC/SoC design tools/techniques, connectivity checks, RTL generation, formal equivalence verification checks, synthesis flows, SystemVerilog programming language, logic design principles, and automation using PERL and Python

Responsibilities

Work closely with architects, peer microarchitects and logic designers
Perform microarchitecture and logic design of SOC functional and performance features
Integrate RTL designs from multiple design areas and IPs
Maintain the RTL model and work with verification engineers to verify the design
Collaborate with chip leads to determine areas for automation and tooling
Apply system, fabric, memory, and SOC architecture knowledge to assess performance impacts and suggest design improvements

Work closely with architects, peer microarchitects and logic designers, verification engineers, and

physical implementation designers to study the architecture specifications and performance features specifications, evaluate their implementation feasibility, tune the features, and write the RTL for the features. Perform the microarchitecture and logic design of the SOC functional and performance features to meet the targets of functionality, performance, timing, area, and power. Integrate the RTL designs from multiple design areas and IPs, regress the integrated models, check the integration requirements, and release models. Focus on methodology and support RTL design. Maintain the RTL model and work with the verification engineers to verify the design and fix the bugs, as well as work with the physical implementors to fix the design for timing and power issues. Collaborate with chip leads to determine other areas to support current or future designs that can benefit from automation and tooling. Apply solid system, fabric, memory, and SOC architecture knowledge to work effectively with physical implementation engineers, verification engineers and architects on assessing the performance impacts from the SOC components and memory subsystem and suggest ideas to improve the overall design.

Education:

Master’s or foreign equivalent in Electrical Engineering or related field (e.g. Electrical and Computer Engineering)

Experience:

3 years of experience in job offered or related occupation

Special Requirements: Must have at least 1 year of prior work experience in each of the following:

Utilizing various ASIC/SoC design tools/techniques, including lint checks, clock and reset domain

crossing etc.

Working with connectivity checks, RTL generation, formal equivalence verification checks and

synthesis flows.

Utilizing SystemVerilog programming language.
Logic design principles with power, performance, timing and area implications.
Automation (using PERL and Python) to enhance the quality of IP handoff and managing design

changes.

**Telecommuting allowed for this position**

Worksite: 3315 Scott Blvd. 4th Floor, Santa Clara, CA 95054

Applicant Instructions: Email resume to: [email protected]. Include job code 88865 in reply. EOE.

Rivos

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Rivos Inc. is ideal for professionals keen on contributing to the frontier of computing technology, specifically within the RISC-V architecture. Emphasizing high-performance systems for the enterprise sector, the company not only offers the opportunity to work on groundbreaking projects but also to grow in a field that demands constant innovation and offers substantial industry impact.

Company Stage

Series A

Total Funding

$370M

Headquarters

Santa Clara, California

Founded

2021

Growth & Insights

Headcount

6 month growth

↑ 3%

1 year growth

↑ 14%

2 year growth

↑ 46%

INACTIVE