SoC Performance Modeling and Verification Engineer

Responsibilities

• As a SoC Performance Modeling and Verification Engineer, you will own or participate in the following:
• Validate the performance model and RTL against the specification and correlate the performance model with RTL
• Develop performance verification test suite and infrastructure to ensure quality of model and design
• Creating traces for SystemVerilog/UVM based testbenches and performance model
• Hands on debugging of performance issues and adding features for transactors in these testbenches
• Work with architecture and design teams to determine performance targets and configurations, and review results
• Provide feedback to the architecture and design teams regarding the micro-architectural choices that may have been made

Requirements

• Proficient in SystemVerilog and waveform debugging tools.
• Knowledge of SW programming with good understanding of C/C++, Python, and modular object oriented software development.
• In-depth knowledge of memory subsystem architecture, microarchitecture and design including caches, cache coherency, NOC, LPDDR/DDR/HBM, PCIe/CXL, Ethernet and IO.
• Strong knowledge in SoC architecture and power/performance trade-offs.
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
• Ability to work collaboratively in a team and be productive under aggressive schedules.

Education and Experience

• Bachelor’s degree plus 5 years of industry experience.
• Master’s degree plus 3 years of industry experience.
• Ph.D with internship experience.