Responsibilities

• Drive the verification of a certain area of performance features in a chip design.
• Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (simulation, emulation and post-silicon)
• Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification
• Develop tests in assembly, C/C++, or vectors to debug and correlate the RTL and performance model
• Develop C/C++/SV based checkers for verifying the performance features
• Develop coverage monitors and analyze coverage to ensure all performance features are covered
• Debug performance issues and conduct performance tuning on silicon

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with vast amount of relevant experience
• Experience with performance modeling, processor verification, or RTL design 
• Experience in developing performance test plans and writing/debugging assembly tests for performance correlation and verification
• Good programming skills in assembly, C/C++, Verilog, System Verilog, and scriptingExperience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
• Strong problem solving and debug skills across various levels of design hierarchies
• Prior experience in industry standard ISAs – ARM, RISC-V, X86 preferred
• Prior experience with instruction profiling and validation on silicon preferred