Responsibilities

• Work closely with the Performance team to analyze power behavior of workloads of interest on Rivos’ architecture
• Define and extend the power management features, to maximize performance on workloads of interest under power and current constraints
• Work closely with micro architecture and design teams to bring the new features to product level quality
• Collaborate with the performance simulation teams to prototype the features and analyze their benefits pre-silicon
• Work closely with the FW and SW teams to integrate the heuristics into the FW code and simulation model
• Assist with post-silicon bringup and characterization of the power-management architecture on RIvos’ devices.

Requirements

• BS/MS degree in CS/CE/EE or equivalent experience
• Experience with CPU/GPU/SoC power-management architecture feature definition such as power capping, thermal control, current capping, and DVFS
• Good understanding of power and/or performance modeling using simulators is preferred
• Ability to work collaboratively in a fast-paced and dynamic environment
• Go-getter capable of initiating and driving tasks from start to finish with minimum technical oversight 

Education and Experience

• BS (5-10 years of experience) or MS (3-5 years of experience) with a degree in CS/CE/EE or equivalent field, The team already includes senior engineers who will collaborate on feature definition and mentoring.