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Senior Ic Layout Mask Designer (Contractor)
Posted on 2/21/2022
Billerica, MA, USA
Experience Level
  • Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys
  • Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools
  • Experience with layout of high performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired
  • Experience with floor planning, block level routing and top level chip assembly
  • Knowledge of high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration
  • Demonstrated experience with analog layout for silicon chips in mass production
  • Experience with FinFET process nodes preferred
  • Experience working with distributed design teams a plus
  • Knowledge of skill code an layout automation a plus
  • Self starter with the ability to define and adhere to a schedule
  • Must possess strong written and verbal communication skills
  • 10+ years experience in high performance analog layout in advanced CMOS process
Omni Design Technologies

11-50 employees

Ultra-low power semiconductor embedded circuits (IP Cores)
Company mission
Omni Design's mission is to provide a wide range of ultra low-power, high performance embedded circuits configured to enable highly-differentiated semiconductor systems and plug-and-play system-on-chip (SoC) development.