Senior CMOS IC Layout Engineer

Digital Verification Engineer (Contractor)

Contract: 3 - 6 Months

Location: Torrance CA, Hybrid (3 days a week)

Competitive hourly rate: $80-$100 per hour

About Claros

Claros innovates at the intersection of power and compute. We build advanced semiconductor power management solutions that improve AI compute capacity, efficiency and reliability. Claros is an early-stage startup company located in Torrance, CA. If you are looking for challenging work and a strong technical environment with the collaborative & supportive culture, then Claros Tech is the company for you. We offer industry the best competitive pay & benefits and early-stage stock options. 

About The Team

We are open-minded, fast paced, problem solvers that value open dialogue and candor. Our passion is to challenge the status-quo and we embrace transformational thinking.  Our response is never “no, but….” instead “yes, if….”.  We are mindful of our personal and organizational blinders and try to build an environment where are team members are At Their Best.

About the Role

We are seeking a highly motivated Digital Verification Engineer to join our team developing digitally integrated circuits for Power Management Integrated Circuits (PMICs). These designs are at the core of high-efficiency energy solutions across a wide range of applications, from mobile and automotive to enterprise and IoT systems.

As a member of the team, you’ll ensure the functional correctness, robustness, and performance of our digital IP blocks and subsystems before silicon tape-out. You’ll work closely with design, architecture, and validation teams to verify critical control logic, digital interfaces, and mixed-signal interactions within the PMIC domain.

While familiarity and experience with UVM (Universal Verification Methodology) is a plus, it is not fully required. We are looking for candidates with a solid foundation in functional verification and a strong interest in working on mission-critical power management designs.

What You Will Do

• Develop, implement, and execute verification plans for digital blocks within PMICs
• Create and maintain test benches, verification environments, and regression tests
• Write directed and constrained-random tests to validate control logic, power state machines, and digital interfaces
• Analyze RTL designs and define appropriate coverage metrics
• Collaborate with analog/mixed-signal teams to verify digital-analog interactions
• Debug design and verification issues, triage simulation failures, and support design closure
• Contribute to verification infrastructure and methodology improvements
• Track and report verification metrics related to HDL code execution & corner cases

What You Will Bring

• BS or MS in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 6-8 years of experience in the field
• Solid understanding of digital logic design (e.g., power control logic, clock/power gating, I²C/SPI/PMBus protocols)
• Experience with Verilog/SystemVerilog and Cadence simulation tools
• Scripting skills (Python, Tcl, Perl, Shell) for automation and regression flows
• Knowledge of power management concepts (LDOs, DCDC converters, sequencing, protection circuits)
• Familiarity with UVM, SystemVerilog classes, or other verification methodologies
• Experience in mixed-signal verification or co-simulation environments

What Is Helpful

• Excellent analytical and debugging skills
• Effective communication and documentation habits
• Proactive, detail-oriented, and committed to high-quality work
• Comfortable working in cross-functional teams and fast-paced environments